• Rodrigo Vivi's avatar
    drm/i915: FBC flush nuke for BDW · c5ad011d
    Rodrigo Vivi authored
    According to spec FBC on BDW and HSW are identical without any gaps.
    So let's copy the nuke and let FBC really start compressing stuff.
    
    Without this patch we can verify with false color that nothing is being
    compressed. With the nuke in place and false color it is possible
    to see false color debugs.
    
    Unfortunatelly on some rings like BCS on BDW we have to avoid Bits 22:18 on
    LRIs due to a high risk of hung. So, when using Blt ring for frontbuffer rend
    cache would never been cleaned and FBC would stop compressing buffer.
    One alternative is to cache clean on software frontbuffer tracking.
    
    v2: Fix rebase conflict.
    v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking.
    Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    c5ad011d
i915_drv.h 88.4 KB