• Laurent Pinchart's avatar
    drm: rcar-du: Fix DU3 start/stop on M3-N · 0bc3544a
    Laurent Pinchart authored
    Group start/stop is controlled by the DRES and DEN bits of DSYSR0 for
    the first group and DSYSR2 for the second group. On most DU instances,
    this maps to the first CRTC of the group. On M3-N, however, DU2 doesn't
    exist, but DSYSR2 does. There is no CRTC object there that maps to the
    correct DSYSR register.
    
    Commit 9144adc5 ("drm: rcar-du: Cache DSYSR value to ensure known
    initial value") switched group start/stop from using group read/write
    access to DSYSR to a CRTC-based API to cache the DSYSR value. While
    doing so, it introduced a regression on M3-N by accessing DSYSR3 instead
    of DSYSR2 to start/stop the second group.
    
    To fix this, access the DSYSR register directly through group read/write
    if the SoC is missing the first DU channel of the group. Keep using the
    rcar_du_crtc_dsysr_clr_set() function otherwise, to retain the DSYSR
    caching feature.
    
    Fixes: 9144adc5 ("drm: rcar-du: Cache DSYSR value to ensure known initial value")
    Reported-by: default avatarHoan Nguyen An <na-hoan@jinso.co.jp>
    Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
    Acked-by: default avatarKieran Bingham <kieran.bingham+renesas@ideasonboard.com>
    Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
    0bc3544a
rcar_du_group.c 8.96 KB