• Torsten Fleischer's avatar
    spi: atmel: Fix interrupt setup for PDC transfers · 76e1d14b
    Torsten Fleischer authored
    Additionally to the current DMA transfer the PDC allows to set up a next DMA
    transfer. This is useful for larger SPI transfers.
    
    The driver currently waits for ENDRX as end of the transfer. But ENDRX is set
    when the current DMA transfer is done (RCR = 0), i.e. it doesn't include the
    next DMA transfer.
    Thus a subsequent SPI transfer could be started although there is currently a
    transfer in progress. This can cause invalid accesses to the SPI slave devices
    and to SPI transfer errors.
    
    This issue has been observed on a hardware with a M25P128 SPI NOR flash.
    
    So instead of ENDRX we should wait for RXBUFF. This flag is set if there is
    no more DMA transfer in progress (RCR = RNCR = 0).
    Signed-off-by: default avatarTorsten Fleischer <torfl6749@gmail.com>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    Cc: stable@vger.kernel.org
    76e1d14b
spi-atmel.c 37.9 KB