• Ravikumar Kattekola's avatar
    ARM: dts: DRA7x: Fix the bypass clock source for dpll_iva and others · d2192ea0
    Ravikumar Kattekola authored
    Fixes: ee6c7507 (ARM: dts: dra7 clock data)
    
    On DRA7x, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
    the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
    But the bypass input is not directly routed to bypass clkout instead
    both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.
    
    This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
    and it's POR value is zero which selects the CLKINP as bypass clkout.
    which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck
    
    Fix this by adding another mux clock as parent in bypass mode.
    
    This design is common to most of the PLLs and the rest have only one bypass
    clock. Below is a list of the DPLLs that need this fix:
    
    DPLL_IVA, DPLL_DDR,
    DPLL_DSP, DPLL_EVE,
    DPLL_GMAC, DPLL_PER,
    DPLL_USB and DPLL_CORE
    Signed-off-by: default avatarRavikumar Kattekola <rk@ti.com>
    Acked-by: default avatarTero Kristo <t-kristo@ti.com>
    Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    d2192ea0
dra7xx-clocks.dtsi 52.5 KB