• Bartlomiej Zolnierkiewicz's avatar
    [PATCH] pdc202xx_old.c: sanitize 66MHz clock use · f154cb92
    Bartlomiej Zolnierkiewicz authored
    Sanitize 66MHz clock use: "enable" 66MHz clock before starting UDMA3/4/5
    read/write transfer and "disable" it after finishing transfer.
    
    - fixes timings for non-UDMA3/4/5 operations (correct 33MHz timings are used)
    
    - allows using UDMA3/4/5 modes on a capable drive even if non-UDMA3/4/5 drive
      is present on the same channel
    
    - fixes corner case when one drive on the channel was using UDMA66/100 + LBA48
      (so clock was enabled/disabled for each read/write) and other one was using
      UDMA66/100 + LBA28, it could happen that request on LBA48 drive disabled
      66MHz clock and it was not enabled for the next transfer on LBA28 drive
    f154cb92
pdc202xx_old.c 28.1 KB