• Stafford Horne's avatar
    openrisc: add tick timer multi-core sync logic · 4553474d
    Stafford Horne authored
    In case timers are not in sync when cpus start (i.e. hot plug / offset
    resets) we need to synchronize the secondary cpus internal timer with
    the main cpu.  This is needed as in OpenRISC SMP there is only one
    clocksource registered which reads from the same ttcr register on each
    cpu.
    
    This synchronization routine heavily borrows from mips implementation that
    does something similar.
    Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
    4553474d
time.c 4.55 KB