staging: rtl8192e: Rework EEPROM handling code
Card configuration is stored in SPI EEPROM (93c46 or 93c56) working in 128|256x16 mode. Communication is handled using GPIO bitbang. >From behaviour perspective, delay after read was removed. It is not needed as we wait after reading GPIO mapped to PCI-E register - it should have no side effects. According to sample EEPROM datasheet (AT93Cx6), max frequency for worst case scenario (1.8V supply) is 250kHZ (vs. 1MHz for 5V). Driver generates ~50kHZ clock - margin should be big enough even for devices from other vendors. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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