Merge nuts.ninka.net:/disk1/davem/BK/network-2.5

into nuts.ninka.net:/disk1/davem/BK/net-2.5

CREDITS

@@ -3461,11 +3461,11 @@ S: Cambridge. CB1 7EG
 S: England
 
 N: Chris Wright
-E: chris@wirex.com
+E: chrisw@osdl.org
 D: hacking on LSM framework and security modules.
-S: c/o WireX
-S: 920 SW 3rd, Ste. 100
-S: Portland, OR 97204
+S: c/o OSDL
+S: 12725 SW Millikan Way, Suite 400
+S: Beaverton, OR 97005
 S: USA
 
 N: Frank Xia

Documentation/as-iosched.txt

+Anticipatory IO scheduler
+-------------------------
+Nick Piggin <piggin@cyberone.com.au>    13 Sep 2003
+
+Attention! Database servers, especially those using "TCQ" disks should
+investigate performance with the 'deadline' IO scheduler. Any system with high
+disk performance requirements should do so, in fact.
+
+If you see unusual performance characteristics of your disk systems, or you
+see big performance regressions versus the deadline scheduler, please email
+me. Database users don't bother unless you're willing to test a lot of patches
+from me ;) its a known issue.
+
+
+Selecting IO schedulers
+-----------------------
+To choose IO schedulers at boot time, use the argument 'elevator=deadline'.
+'noop' and 'as' (the default) are also available. IO schedulers are assigned
+globally at boot time only presently.
+
+
+Tuning the anticipatory IO scheduler
+------------------------------------
+When using 'as', the anticipatory IO scheduler there are 5 parameters under
+/sys/block/*/iosched/. All are units of milliseconds.
+
+The parameters are:
+* read_expire
+    Controls how long until a request becomes "expired". It also controls the
+    interval between which expired requests are served, so set to 50, a request
+    might take anywhere < 100ms to be serviced _if_ it is the next on the
+    expired list. Obviously it won't make the disk go faster. The result
+    basically equates to the timeslice a single reader gets in the presence of
+    other IO. 100*((seek time / read_expire) + 1) is very roughly the %
+    streaming read efficiency your disk should get with multiple readers.
+    
+* read_batch_expire
+    Controls how much time a batch of reads is given before pending writes are
+    served. Higher value is more efficient. This might be set below read_expire
+    if writes are to be given higher priority than reads, but reads are to be
+    as efficient as possible when there are no writes. Generally though, it
+    should be some multiple of read_expire.
+   
+* write_expire, and
+* write_batch_expire are equivalent to the above, for writes.
+
+* antic_expire
+    Controls the maximum amount of time we can anticipate a good read before
+    giving up. Many other factors may cause anticipation to be stopped early,
+    or some processes will not be "anticipated" at all. Should be a bit higher
+    for big seek time devices though not a linear correspondence - most
+    processes have only a few ms thinktime.
+

MAINTAINERS

@@ -169,8 +169,8 @@ W:	http://domsch.com/linux
 S:	Supported
 
 ACPI
-P:	Andy Grover
-M:	andrew.grover@intel.com
+P:	Len Brown
+M:	len.brown@intel.com
 L:	acpi-devel@lists.sourceforge.net
 W:	http://sf.net/projects/acpi/
 S:	Maintained
@@ -1207,6 +1207,13 @@ W:	http://linuxppc64.org
 L:	linuxppc64-dev@lists.linuxppc.org
 S:	Supported
 
+LINUX SECURITY MODULE (LSM) FRAMEWORK
+P:	Chris Wright
+M:	chrisw@osdl.org
+L:	linux-security-module@wirex.com
+W:	http://lsm.immunix.org
+S:	Supported
+
 LOGICAL DISK MANAGER SUPPORT (LDM, Windows 2000/XP Dynamic Disks)
 P:	Richard Russon (FlatCap)
 M:	ldm@flatcap.org

arch/arm/Kconfig

@@ -213,198 +213,7 @@ config FORCE_MAX_ZONEORDER
 	depends on SA1111
 	default "9"
 
-comment "Processor Type"
-
-# Figure out whether this system uses 26-bit or 32-bit CPUs.
-config CPU_32
-	bool
-	default y
-
-# Select CPU types depending on the architecture selected.  This selects
-# which CPUs we support in the kernel image, and the compiler instruction
-# optimiser behaviour.
-# ARM610
-config CPU_ARM610
-	bool "Support ARM610 processor"
-	depends on ARCH_RPC
-	help
-	  The ARM610 is the successor to the ARM3 processor
-	  and was produced by VLSI Technology Inc.
-
-	  Say Y if you want support for the ARM610 processor.
-	  Otherwise, say N.
-
-# ARM710
-config CPU_ARM710
-	bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
-	default y if ARCH_CLPS7500
-	help
-	  A 32-bit RISC microprocessor based on the ARM7 processor core
-	  designed by Advanced RISC Machines Ltd. The ARM710 is the
-	  successor to the ARM610 processor. It was released in
-	  July 1994 by VLSI Technology Inc.
-
-	  Say Y if you want support for the ARM710 processor.
-	  Otherwise, say N.
-
-# ARM720T
-config CPU_ARM720T
-	bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
-	default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712
-	help
-	  A 32-bit RISC processor with 8kByte Cache, Write Buffer and
-	  MMU built around an ARM7TDMI core.
-
-	  Say Y if you want support for the ARM720T processor.
-	  Otherwise, say N.
-
-# ARM920T
-config CPU_ARM920T
-	bool "Support ARM920T processor"
-	depends on ARCH_INTEGRATOR
-	help
-	  The ARM920T is licensed to be produced by numerous vendors,
-	  and is used in the Maverick EP9312.  More information at
-	  <http://linuxdevices.com/products/PD2382866068.html>.
-
-	  Say Y if you want support for the ARM920T processor.
-	  Otherwise, say N.
-
-# ARM922T
-config CPU_ARM922T
-	bool
-	depends on ARCH_CAMELOT
-	default y
-	help
-	  The ARM922T is a version of the ARM920T, but with smaller
-	  instruction and data caches. It is used in Altera's
-	  Excalibur XA device family.
-
-	  Say Y if you want support for the ARM922T processor.
-	  Otherwise, say N.
-
-# ARM926T
-config CPU_ARM926T
-	bool "Support ARM926T processor"
-	depends on ARCH_INTEGRATOR
-	help
-	  This is a variant of the ARM920.  It has slightly different
-	  instruction sequences for cache and TLB operations.  Curiously,
-	  there is no documentation on it at the ARM corporate website.
-
-	  Say Y if you want support for the ARM926T processor.
-	  Otherwise, say N.
-
-# ARM1020
-config CPU_ARM1020
-	bool "Support ARM1020 processor"
-	depends on ARCH_INTEGRATOR
-	help
-	  The ARM1020 is the cached version of the ARM10 processor,
-	  with an addition of a floating-point unit.
-
-	  Say Y if you want support for the ARM1020 processor.
-	  Otherwise, say N.
-
-# SA110
-config CPU_SA110
-	bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && !ARCH_ANAKIN && ARCH_RPC
-	default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI || ARCH_ANAKIN
-	help
-	  The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
-	  is available at five speeds ranging from 100 MHz to 233 MHz.
-	  More information is available at
-	  <http://developer.intel.com/design/strong/sa110.htm>.
-
-	  Say Y if you want support for the SA-110 processor.
-	  Otherwise, say N.
-
-# SA1100
-config CPU_SA1100
-	bool
-	depends on ARCH_SA1100
-	default y
-
-# XScale
-config CPU_XSCALE
-	bool
-	depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA
-	default y
-
-# Figure out what processor architecture version we should be using.
-# This defines the compiler instruction set which depends on the machine type.
-config CPU_32v3
-	bool
-	depends on ARCH_RPC || ARCH_CLPS7500
-	default y
-
-config CPU_32v4
-	bool
-	depends on ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI || ARCH_CLPS711X || ARCH_INTEGRATOR || ARCH_SA1100 || ARCH_L7200 || ARCH_ANAKIN || ARCH_CAMELOT
-	default y
-
-config CPU_32v5
-	bool
-	depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA
-	default y
-
-comment "Processor Features"
-
-config ARM_THUMB
-	bool "Support Thumb instructions (EXPERIMENTAL)"
-	depends on (CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020 || CPU_XSCALE) && EXPERIMENTAL
-	help
-	  Say Y if you want to have kernel support for ARM Thumb instructions,
-	  fault handlers, and system calls.
-
-	  The Thumb instruction set is a compressed form of the standard ARM
-	  instruction set resulting in smaller binaries at the expense of
-	  slightly less efficient code.
-
-	  If you don't know what this all is, saying Y is a safe choice.
-
-config CPU_BIG_ENDIAN
-	bool "Build big-endian kernel"
-	depends on ARCH_SUPPORTS_BIG_ENDIAN
-	help
-	  Say Y if you plan on running a kernel in big-endian mode.
-	  Note that your board must be properly built and your board
-	  port must properly enable and big-endian related features
-	  of your chipset/board/processor.
-
-config CPU_ICACHE_DISABLE
-	bool "Disable I-Cache"
-	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020
-	help
-	  Say Y here to disable the processor instruction cache. Unless
-	  you have a reason not to or are unsure, say N.
-
-config CPU_DCACHE_DISABLE
-	bool "Disable D-Cache"
-	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020
-	help
-	  Say Y here to disable the processor data cache. Unless
-	  you have a reason not to or are unsure, say N.
-
-config CPU_DCACHE_WRITETHROUGH
-	bool "Force write through D-cache"
-	depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
-	help
-	  Say Y here to use the data cache in writethough mode. Unless you
-	  specifically require this or are unsure, say N.
-
-config CPU_CACHE_ROUND_ROBIN
-	bool "Round robin I and D cache replacement algorithm"
-	depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
-	help
-	  Say Y here to use the predictable round-robin cache replacement
-	  policy.  Unless you specifically require this or are unsure, say N.
-
-config CPU_BPREDICT_DISABLE
-	bool "Disable branch prediction"
-	depends on CPU_ARM1020
-	help
-	  Say Y here to disable branch prediction.  If unsure, say N.
+source arch/arm/mm/Kconfig
 
 #  bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
 config XSCALE_PMU
@@ -842,11 +651,6 @@ source "drivers/input/Kconfig"
 
 source "drivers/char/Kconfig"
 
-config KBDMOUSE
-	bool
-	depends on ARCH_ACORN && BUSMOUSE=y && !ARCH_RPC
-	default y
-
 source "drivers/media/Kconfig"
 
 source "fs/Kconfig"

arch/arm/Makefile

@@ -172,22 +172,6 @@ bp:;	$(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage
 i:;	$(Q)$(MAKE) $(build)=$(boot) install
 zi:;	$(Q)$(MAKE) $(build)=$(boot) zinstall
 
-#
-# Configuration targets.  Use these to select a
-# configuration for your architecture
-%_config:
-	@( \
-	CFG=$(@:_config=); \
-	if [ -f arch/arm/def-configs/$$CFG ]; then \
-	  [ -f .config ] && mv -f .config .config.old; \
-	  cp arch/arm/def-configs/$$CFG .config; \
-	  echo "*** Default configuration for $$CFG installed"; \
-	  echo "*** Next, you may run 'make oldconfig'"; \
-	else \
-	  echo "$$CFG does not exist"; \
-	fi; \
-	)
-
 arch/$(ARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \
 				   include/asm-arm/.arch \
 				   include/config/MARKER

arch/arm/boot/bootp/init.S

 /*
  *  linux/arch/arm/boot/bootp/init.S
  *
- *  Copyright (C) 2000-2002 Russell King
+ *  Copyright (C) 2000-2003 Russell King.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- *  Header file for splitting kernel + initrd.  Note that we pass
+ *  "Header" file for splitting kernel + initrd.  Note that we pass
  *  r0 through to r3 straight through.
+ *
+ *  This demonstrates how to append code to the start of the kernel
+ *  zImage, and boot the kernel without copying it around.  This
+ *  example would be simpler; if we didn't have an object of unknown
+ *  size immediately following the kernel, we could build this into
+ *  a binary blob, and concatenate the zImage using the cat command.
  */
 		.section .start,#alloc,#execinstr
 		.type	_start, #function
 		.globl	_start
-_start:		adr	r10, initdata
-		ldr	r11, initdata
-		sub	r11, r10, r11		@ work out exec offset
-		b	splitify
-		.size	_entry,. - _entry
-
-		.type	initdata, #object
-initdata:	.word	initdata		@ compiled address of this
-		.size	initdata,. - initdata
 
-splitify:	adr	r13, data
-		ldmia	r13!, {r4-r6}		@ move the initrd
-		add	r4, r4, r11		@ correction
-		bl	move
+_start:		adr	r12, kernel_start	@ offset of kernel zImage
+		ldr	r4, [r12, #0x2c]	@ length of zImage
+		adr	r13, data
+		add	r4, r4, r12		@ end of zImage, start of initrd
+		ldmia	r13!, {r5-r6}		@ r5 = dest, r6 = length
+		bl	move			@ move the initrd
 
 /*
- * Setup the initrd parameters to pass to the kernel.  This can either be
- * passed in via a param_struct or a tag list.  We spot the param_struct
- * method by looking at the first word; this should either indicate a page
- * size of 4K, 16K or 32K.
+ * Setup the initrd parameters to pass to the kernel.  This can only be
+ * passed in via the tagged list.
  */
-		ldmia	r13, {r4-r8}		@ get size and addr of initrd
-						@ r5 = ATAG_INITRD
-						@ r6 = initrd start
-						@ r7 = initrd end
-						@ r8 = param_struct address
-		ldr	r9, [r8, #0]		@ no param struct?
-		teq	r9, #0x1000		@ 4K?
-		teqne	r9, #0x4000		@ 16K?
-		teqne	r9, #0x8000		@ 32K?
-		beq	param_struct
-
-		ldr	r9, [r8, #4]		@ get first tag
-		teq	r9, r4
-		bne	taglist			@ ok, we have a tag list
+		ldmia	r13, {r5-r9}		@ get size and addr of initrd
+						@ r5 = ATAG_CORE
+						@ r6 = ATAG_INITRD2
+						@ r7 = initrd start
+						@ r8 = initrd end
+						@ r9 = param_struct address
 
+		ldr	r10, [r9, #4]		@ get first tag
+		teq	r10, r5			@ is it ATAG_CORE?
 /*
- * We didn't find a valid tag list - create one.
+ * If we didn't find a valid tag list, create a dummy ATAG_CORE entry.
  */
-		str	r4, [r8, #4]
-		mov	r4, #8
-		str	r4, [r8, #0]
-		mov	r4, #0
-		str	r4, [r8, #8]
+		movne	r10, #0			@ terminator
+		movne	r4, #2			@ Size of this entry (2 words)
+		stmneia	r8, {r4, r5, r10}	@ Size, ATAG_CORE, terminator
 
 /*
  * find the end of the tag list, and then add an INITRD tag on the end.
  * If there is already an INITRD tag, then we ignore it; the last INITRD
  * tag takes precidence.
  */
-taglist:	ldr	r9, [r8, #0]		@ tag length
-		teq	r9, #0			@ last tag?
-		addne	r8, r8, r9
+taglist:	ldr	r10, [r9, #0]		@ tag length
+		teq	r10, #0			@ last tag (zero length)?
+		addne	r9, r9, r10, lsl #2
 		bne	taglist
 
-		mov	r4, #16			@ length of initrd tag
-		mov	r9, #0			@ end of tag list terminator
-		stmia	r8, {r4, r5, r6, r7, r9}
-		adr	r12, kernel_start
+		mov	r5, #4			@ Size of initrd tag (4 words)
+		stmia	r9, {r5, r6, r7, r8, r10}
 		mov	pc, r12			@ call kernel
 
 /*
- * We found a param struct.  Modify the param struct for the initrd
+ * Move the block of memory length r6 from address r4 to address r5
  */
-param_struct:	add	r8, r8, #16*4
-		stmia	r8, {r6,r7}		@ save in param_struct
-		mov	pc, r12			@ call kernel
-
 move:		ldmia	r4!, {r7 - r10}		@ move 32-bytes at a time
 		stmia	r5!, {r7 - r10}
 		ldmia	r4!, {r7 - r10}
@@ -89,15 +72,18 @@ move:		ldmia	r4!, {r7 - r10}		@ move 32-bytes at a time
 		bcs	move
 		mov	pc, lr
 
-data:		.word	initrd_start
-		.word	initrd_addr
-		.word	initrd_len
+		.size	_start, . - _start
+
+		.type	data,#object
+data:		.word	initrd_addr		@ destination initrd address
+		.word	initrd_len		@ initrd size
 
 		.word	0x54410001		@ r4 = ATAG_CORE
-		.word	0x54420005		@ r5 = ATAG_INITRD
+		.word	0x54420005		@ r5 = ATAG_INITRD2
 		.word	initrd_addr		@ r6
 		.word	initrd_len		@ r7
 		.word	params			@ r8
+		.size	data, . - _data
 
 		.type	initrd_start,#object
 

arch/arm/boot/compressed/head-sa1100.S

@@ -34,7 +34,7 @@ __SA1100_start:
 		@ REVISIT_PFS168: Temporary until firmware updated to use assigned machine number
 		mov	r7, #MACH_TYPE_PFS168
 #endif
-#ifdef CONFIG_SA1100_SIMPAD /
+#ifdef CONFIG_SA1100_SIMPAD
 		@ UNTIL we've something like an open bootldr
 		mov	r7, #MACH_TYPE_SIMPAD @should be 87
 #endif

arch/arm/common/sa1111-pcipool.c

@@ -51,7 +51,7 @@ struct pci_page {	/* cacheable header for 'allocation' bytes */
 
 static inline const char *slot_name(const struct pci_pool *pool)
 {
-	const struct pci_dev *pdev = pool->dev;
+	struct pci_dev *pdev = (struct pci_dev *)pool->dev;
 
 	if (pdev == 0)
 		return "[0]";

arch/arm/common/sa1111.c

@@ -54,87 +54,74 @@ struct sa1111 {
  */
 static struct sa1111 *g_sa1111;
 
-static struct sa1111_dev usb_dev = {
-	.skpcr_mask	= SKPCR_UCLKEN,
-	.devid		= SA1111_DEVID_USB,
-	.irq = {
-		IRQ_USBPWR,
-		IRQ_HCIM,
-		IRQ_HCIBUFFACC,
-		IRQ_HCIRMTWKP,
-		IRQ_NHCIMFCIR,
-		IRQ_USB_PORT_RESUME
-	},
+struct sa1111_dev_info {
+	unsigned long	offset;
+	unsigned long	skpcr_mask;
+	unsigned int	devid;
+	unsigned int	irq[6];
 };
 
-static struct sa1111_dev sac_dev = {
-	.skpcr_mask	= SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
-	.devid		= SA1111_DEVID_SAC,
-	.irq = {
-		AUDXMTDMADONEA,
-		AUDXMTDMADONEB,
-		AUDRCVDMADONEA,
-		AUDRCVDMADONEB
+static struct sa1111_dev_info sa1111_devices[] = {
+	{
+		.offset		= SA1111_USB,
+		.skpcr_mask	= SKPCR_UCLKEN,
+		.devid		= SA1111_DEVID_USB,
+		.irq = {
+			IRQ_USBPWR,
+			IRQ_HCIM,
+			IRQ_HCIBUFFACC,
+			IRQ_HCIRMTWKP,
+			IRQ_NHCIMFCIR,
+			IRQ_USB_PORT_RESUME
+		},
 	},
-};
-
-static struct sa1111_dev ssp_dev = {
-	.skpcr_mask	= SKPCR_SCLKEN,
-	.devid		= SA1111_DEVID_SSP,
-};
-
-static struct sa1111_dev kbd_dev = {
-	.skpcr_mask	= SKPCR_PTCLKEN,
-	.devid		= SA1111_DEVID_PS2,
-	.irq = {
-		IRQ_TPRXINT,
-		IRQ_TPTXINT
+	{
+		.offset		= 0x0600,
+		.skpcr_mask	= SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
+		.devid		= SA1111_DEVID_SAC,
+		.irq = {
+			AUDXMTDMADONEA,
+			AUDXMTDMADONEB,
+			AUDRCVDMADONEA,
+			AUDRCVDMADONEB
+		},
 	},
-};
-
-static struct sa1111_dev mse_dev = {
-	.skpcr_mask	= SKPCR_PMCLKEN,
-	.devid		= SA1111_DEVID_PS2,
-	.irq = {
-		IRQ_MSRXINT,
-		IRQ_MSTXINT
+	{
+		.offset		= 0x0800,
+		.skpcr_mask	= SKPCR_SCLKEN,
+		.devid		= SA1111_DEVID_SSP,
 	},
-};
-
-static struct sa1111_dev int_dev = {
-	.skpcr_mask	= 0,
-	.devid		= SA1111_DEVID_INT,
-};
-
-static struct sa1111_dev pcmcia_dev = {
-	.skpcr_mask	= 0,
-	.devid		= SA1111_DEVID_PCMCIA,
-	.irq = {
-		IRQ_S0_READY_NINT,
-		IRQ_S0_CD_VALID,
-		IRQ_S0_BVD1_STSCHG,
-		IRQ_S1_READY_NINT,
-		IRQ_S1_CD_VALID,
-		IRQ_S1_BVD1_STSCHG,
+	{
+		.offset		= SA1111_KBD,
+		.skpcr_mask	= SKPCR_PTCLKEN,
+		.devid		= SA1111_DEVID_PS2,
+		.irq = {
+			IRQ_TPRXINT,
+			IRQ_TPTXINT
+		},
+	},
+	{
+		.offset		= SA1111_MSE,
+		.skpcr_mask	= SKPCR_PMCLKEN,
+		.devid		= SA1111_DEVID_PS2,
+		.irq = {
+			IRQ_MSRXINT,
+			IRQ_MSTXINT
+		},
+	},
+	{
+		.offset		= 0x1800,
+		.skpcr_mask	= 0,
+		.devid		= SA1111_DEVID_PCMCIA,
+		.irq = {
+			IRQ_S0_READY_NINT,
+			IRQ_S0_CD_VALID,
+			IRQ_S0_BVD1_STSCHG,
+			IRQ_S1_READY_NINT,
+			IRQ_S1_CD_VALID,
+			IRQ_S1_BVD1_STSCHG,
+		},
 	},
-};
-
-static struct sa1111_dev *devs[] = {
-	&usb_dev,
-	&sac_dev,
-	&ssp_dev,
-	&kbd_dev,
-	&mse_dev,
-	&pcmcia_dev,
-};
-
-static unsigned int dev_offset[] = {
-	SA1111_USB,
-	0x0600,
-	0x0800,
-	SA1111_KBD,
-	SA1111_MSE,
-	0x1800,
 };
 
 /*
@@ -372,44 +359,45 @@ static struct irqchip sa1111_high_chip = {
 	.wake		= sa1111_wake_highirq,
 };
 
-static void __init sa1111_init_irq(struct sa1111_dev *sadev)
+static void sa1111_setup_irq(struct sa1111 *sachip)
 {
+	void *irqbase = sachip->base + SA1111_INTC;
 	unsigned int irq;
 
 	/*
 	 * We're guaranteed that this region hasn't been taken.
 	 */
-	request_mem_region(sadev->res.start, 512, "irqs");
+	request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
 
 	/* disable all IRQs */
-	sa1111_writel(0, sadev->mapbase + SA1111_INTEN0);
-	sa1111_writel(0, sadev->mapbase + SA1111_INTEN1);
-	sa1111_writel(0, sadev->mapbase + SA1111_WAKEEN0);
-	sa1111_writel(0, sadev->mapbase + SA1111_WAKEEN1);
+	sa1111_writel(0, irqbase + SA1111_INTEN0);
+	sa1111_writel(0, irqbase + SA1111_INTEN1);
+	sa1111_writel(0, irqbase + SA1111_WAKEEN0);
+	sa1111_writel(0, irqbase + SA1111_WAKEEN1);
 
 	/*
 	 * detect on rising edge.  Note: Feb 2001 Errata for SA1111
 	 * specifies that S0ReadyInt and S1ReadyInt should be '1'.
 	 */
-	sa1111_writel(0, sadev->mapbase + SA1111_INTPOL0);
+	sa1111_writel(0, irqbase + SA1111_INTPOL0);
 	sa1111_writel(SA1111_IRQMASK_HI(IRQ_S0_READY_NINT) |
 		      SA1111_IRQMASK_HI(IRQ_S1_READY_NINT),
-		      sadev->mapbase + SA1111_INTPOL1);
+		      irqbase + SA1111_INTPOL1);
 
 	/* clear all IRQs */
-	sa1111_writel(~0, sadev->mapbase + SA1111_INTSTATCLR0);
-	sa1111_writel(~0, sadev->mapbase + SA1111_INTSTATCLR1);
+	sa1111_writel(~0, irqbase + SA1111_INTSTATCLR0);
+	sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
 
 	for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
 		set_irq_chip(irq, &sa1111_low_chip);
-		set_irq_chipdata(irq, sadev->mapbase);
+		set_irq_chipdata(irq, irqbase);
 		set_irq_handler(irq, do_edge_IRQ);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 	}
 
 	for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
 		set_irq_chip(irq, &sa1111_high_chip);
-		set_irq_chipdata(irq, sadev->mapbase);
+		set_irq_chipdata(irq, irqbase);
 		set_irq_handler(irq, do_edge_IRQ);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 	}
@@ -417,9 +405,9 @@ static void __init sa1111_init_irq(struct sa1111_dev *sadev)
 	/*
 	 * Register SA1111 interrupt
 	 */
-	set_irq_type(sadev->irq[0], IRQT_RISING);
-	set_irq_data(sadev->irq[0], sadev->mapbase);
-	set_irq_chained_handler(sadev->irq[0], sa1111_irq_handler);
+	set_irq_type(sachip->irq, IRQT_RISING);
+	set_irq_data(sachip->irq, irqbase);
+	set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
 }
 
 /*
@@ -529,37 +517,64 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
 
 #endif
 
-static void
+static void sa1111_dev_release(struct device *_dev)
+{
+	struct sa1111_dev *dev = SA1111_DEV(_dev);
+
+	release_resource(&dev->res);
+	kfree(dev);
+}
+
+static int
 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
-		      struct sa1111_dev *sadev, unsigned int offset)
+		      struct sa1111_dev_info *info)
 {
-	snprintf(sadev->dev.bus_id, sizeof(sadev->dev.bus_id),
-		 "%4.4x", offset);
+	struct sa1111_dev *dev;
+	int ret;
+
+	dev = kmalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
+	if (!dev) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	memset(dev, 0, sizeof(struct sa1111_dev));
+
+	snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
+		 "%4.4lx", info->offset);
 
 	/*
 	 * If the parent device has a DMA mask associated with it,
 	 * propagate it down to the children.
 	 */
 	if (sachip->dev->dma_mask) {
-		sadev->dma_mask = *sachip->dev->dma_mask;
-		sadev->dev.dma_mask = &sadev->dma_mask;
+		dev->dma_mask = *sachip->dev->dma_mask;
+		dev->dev.dma_mask = &dev->dma_mask;
 	}
 
-	sadev->dev.parent = sachip->dev;
-	sadev->dev.bus    = &sa1111_bus_type;
-	sadev->res.start  = sachip->phys + offset;
-	sadev->res.end    = sadev->res.start + 511;
-	sadev->res.name   = sadev->dev.bus_id;
-	sadev->res.flags  = IORESOURCE_MEM;
-	sadev->mapbase    = sachip->base + offset;
-
-	if (request_resource(parent, &sadev->res)) {
+	dev->devid	 = info->devid;
+	dev->dev.parent  = sachip->dev;
+	dev->dev.bus     = &sa1111_bus_type;
+	dev->dev.release = sa1111_dev_release;
+	dev->res.start   = sachip->phys + info->offset;
+	dev->res.end     = dev->res.start + 511;
+	dev->res.name    = dev->dev.bus_id;
+	dev->res.flags   = IORESOURCE_MEM;
+	dev->mapbase     = sachip->base + info->offset;
+
+	ret = request_resource(parent, &dev->res);
+	if (ret) {
 		printk("SA1111: failed to allocate resource for %s\n",
-			sadev->res.name);
-		return;
+			dev->res.name);
+		goto out;
 	}
 
-	device_register(&sadev->dev);
+	ret = device_register(&dev->dev);
+	if (ret) {
+		release_resource(&dev->res);
+ out:
+		kfree(dev);
+	}
+	return ret;
 }
 
 /**
@@ -655,11 +670,8 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
 	 * The interrupt controller must be initialised before any
 	 * other device to ensure that the interrupts are available.
 	 */
-	if (irq != NO_IRQ) {
-		int_dev.irq[0] = irq;
-		sa1111_init_one_child(sachip, mem, &int_dev, SA1111_INTC);
-		sa1111_init_irq(&int_dev);
-	}
+	if (sachip->irq != NO_IRQ)
+		sa1111_setup_irq(sachip);
 
 	g_sa1111 = sachip;
 
@@ -670,9 +682,9 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
 	else
 		has_devs &= ~(1 << 1);
 
-	for (i = 0; i < ARRAY_SIZE(devs); i++)
+	for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
 		if (has_devs & (1 << i))
-			sa1111_init_one_child(sachip, mem, devs[i], dev_offset[i]);
+			sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
 
 	return 0;
 
@@ -685,11 +697,26 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
 
 static void __sa1111_remove(struct sa1111 *sachip)
 {
-	int i;
+	struct list_head *l, *n;
+	void *irqbase = sachip->base + SA1111_INTC;
+
+	list_for_each_safe(l, n, &sachip->dev->children) {
+		struct device *d = list_to_dev(l);
+
+		device_unregister(d);
+	}
+
+	/* disable all IRQs */
+	sa1111_writel(0, irqbase + SA1111_INTEN0);
+	sa1111_writel(0, irqbase + SA1111_INTEN1);
+	sa1111_writel(0, irqbase + SA1111_WAKEEN0);
+	sa1111_writel(0, irqbase + SA1111_WAKEEN1);
+
+	if (sachip->irq != NO_IRQ) {
+		set_irq_chained_handler(sachip->irq, NULL);
+		set_irq_data(sachip->irq, NULL);
 
-	for (i = 0; i < ARRAY_SIZE(devs); i++) {
-		put_device(&devs[i]->dev);
-		release_resource(&devs[i]->res);
+		release_mem_region(sachip->phys + SA1111_INTC, 512);
 	}
 
 	iounmap(sachip->base);

arch/arm/kernel/asm-offsets.c

@@ -15,9 +15,6 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 
-#include <asm/pgtable.h>
-#include <asm/uaccess.h>
-
 /*
  * Make sure that the compiler and target are compatible.
  */
@@ -58,19 +55,6 @@ int main(void)
   BLANK();
   DEFINE(VM_EXEC,	       	VM_EXEC);
   BLANK();
-  DEFINE(HPTE_TYPE_SMALL,      	PTE_TYPE_SMALL);
-  DEFINE(HPTE_AP_READ,		PTE_AP_READ);
-  DEFINE(HPTE_AP_WRITE,		PTE_AP_WRITE);
-  BLANK();
-  DEFINE(LPTE_PRESENT,		L_PTE_PRESENT);
-  DEFINE(LPTE_YOUNG,		L_PTE_YOUNG);
-  DEFINE(LPTE_BUFFERABLE,      	L_PTE_BUFFERABLE);
-  DEFINE(LPTE_CACHEABLE,       	L_PTE_CACHEABLE);
-  DEFINE(LPTE_USER,		L_PTE_USER);
-  DEFINE(LPTE_WRITE,		L_PTE_WRITE);
-  DEFINE(LPTE_EXEC,		L_PTE_EXEC);
-  DEFINE(LPTE_DIRTY,		L_PTE_DIRTY);
-  BLANK();
   DEFINE(PAGE_SZ,	       	PAGE_SIZE);
   BLANK();
   DEFINE(SYS_ERROR0,		0x9f0000);

arch/arm/kernel/bios32.c

@@ -35,18 +35,17 @@ void pcibios_report_status(u_int status_mask, int warn)
 			continue;
 
 		pci_read_config_word(dev, PCI_STATUS, &status);
+		if (status == 0xffff)
+			continue;
 
-		status &= status_mask;
-		if (status == 0)
+		if ((status & status_mask) == 0)
 			continue;
 
 		/* clear the status errors */
-		pci_write_config_word(dev, PCI_STATUS, status);
+		pci_write_config_word(dev, PCI_STATUS, status & status_mask);
 
 		if (warn)
-			printk("(%02x:%02x.%d: %04X) ", dev->bus->number,
-				PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
-				status);
+			printk("(%s: %04X) ", pci_name(dev), status);
 	}
 }
 

arch/arm/kernel/entry-armv.S

@@ -729,7 +729,7 @@ __dabt_svc:	sub	sp, sp, #S_FRAME_SIZE
  * This routine must not corrupt r9
  */
 #ifdef MULTI_ABORT
-		ldr	r4, .LCprocfns			@ pass r0, r3 to
+		ldr	r4, .LCprocfns			@ pass r2, r3 to
 		mov	lr, pc				@ processor code
 		ldr	pc, [r4]			@ call processor specific code
 #else
@@ -871,7 +871,7 @@ __dabt_usr:	sub	sp, sp, #S_FRAME_SIZE		@ Allocate frame size in one go
 		alignment_trap r7, r7, __temp_abt
 		zero_fp
 #ifdef MULTI_ABORT
-		ldr	r4, .LCprocfns			@ pass r0, r3 to
+		ldr	r4, .LCprocfns			@ pass r2, r3 to
 		mov	lr, pc				@ processor code
 		ldr	pc, [r4]			@ call processor specific code
 #else

arch/arm/kernel/setup.c

@@ -798,7 +798,7 @@ static int c_show(struct seq_file *m, void *v)
 			seq_printf(m, "Cache type\t: %s\n"
 				      "Cache clean\t: %s\n"
 				      "Cache lockdown\t: %s\n"
-				      "Cache unified\t: %s\n",
+				      "Cache format\t: %s\n",
 				   cache_types[CACHE_TYPE(cache_info)],
 				   cache_clean[CACHE_TYPE(cache_info)],
 				   cache_lockdown[CACHE_TYPE(cache_info)],

arch/arm/lib/io-readsb.S

@@ -9,7 +9,6 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/hardware.h>
 
 .insb_align:	rsb	ip, ip, #4
 		cmp	ip, r2
@@ -37,32 +36,36 @@ ENTRY(__raw_readsb)
 
 .insb_16_lp:	ldrb	r3, [r0]
 		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #8
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #16
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #24
-		ldrb	r4, [r0]
-		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #8
-		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #16
-		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #24
 		ldrb	r5, [r0]
+		mov	r3, r3,     lsl #byte(0)
 		ldrb	r6, [r0]
-		orr	r5, r5, r6, lsl #8
-		ldrb	r6, [r0]
-		orr	r5, r5, r6, lsl #16
+		orr	r3, r3, r4, lsl #byte(1)
+		ldrb	r4, [r0]
+		orr	r3, r3, r5, lsl #byte(2)
+		ldrb	r5, [r0]
+		orr	r3, r3, r6, lsl #byte(3)
 		ldrb	r6, [r0]
-		orr	r5, r5, r6, lsl #24
+		mov	r4, r4,     lsl #byte(0)
+		ldrb	ip, [r0]
+		orr	r4, r4, r5, lsl #byte(1)
+		ldrb	r5, [r0]
+		orr	r4, r4, r6, lsl #byte(2)
 		ldrb	r6, [r0]
+		orr	r4, r4, ip, lsl #byte(3)
 		ldrb	ip, [r0]
-		orr	r6, r6, ip, lsl #8
+		mov	r5, r5,     lsl #byte(0)
+		ldrb	lr, [r0]
+		orr	r5, r5, r6, lsl #byte(1)
+		ldrb	r6, [r0]
+		orr	r5, r5, ip, lsl #byte(2)
 		ldrb	ip, [r0]
-		orr	r6, r6, ip, lsl #16
+		orr	r5, r5, lr, lsl #byte(3)
+		ldrb	lr, [r0]
+		mov	r6, r6,     lsl #byte(0)
+		orr	r6, r6, ip, lsl #byte(1)
 		ldrb	ip, [r0]
-		orr	r6, r6, ip, lsl #24
+		orr	r6, r6, lr, lsl #byte(2)
+		orr	r6, r6, ip, lsl #byte(3)
 		stmia	r1!, {r3 - r6}
 
 		subs	r2, r2, #16
@@ -76,18 +79,20 @@ ENTRY(__raw_readsb)
 
 		ldrb	r3, [r0]
 		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #8
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #16
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #24
-		ldrb	r4, [r0]
 		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #8
-		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #16
+		mov	r3, r3,     lsl #byte(0)
+		ldrb	r6, [r0]
+		orr	r3, r3, r4, lsl #byte(1)
+		ldrb	r4, [r0]
+		orr	r3, r3, r5, lsl #byte(2)
 		ldrb	r5, [r0]
-		orr	r4, r4, r5, lsl #24
+		orr	r3, r3, r6, lsl #byte(3)
+		ldrb	r6, [r0]
+		mov	r4, r4,     lsl #byte(0)
+		ldrb	ip, [r0]
+		orr	r4, r4, r5, lsl #byte(1)
+		orr	r4, r4, r6, lsl #byte(2)
+		orr	r4, r4, ip, lsl #byte(3)
 		stmia	r1!, {r3, r4}
 
 .insb_no_8:	tst	r2, #4
@@ -95,11 +100,12 @@ ENTRY(__raw_readsb)
 
 		ldrb	r3, [r0]
 		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #8
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #16
-		ldrb	r4, [r0]
-		orr	r3, r3, r4, lsl #24
+		ldrb	r5, [r0]
+		ldrb	r6, [r0]
+		mov	r3, r3,     lsl #byte(0)
+		orr	r3, r3, r4, lsl #byte(1)
+		orr	r3, r3, r5, lsl #byte(2)
+		orr	r3, r3, r6, lsl #byte(3)
 		str	r3, [r1], #4
 
 .insb_no_4:	ands	r2, r2, #3

arch/arm/lib/io-writesb.S

@@ -9,7 +9,26 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/hardware.h>
+
+		.macro	outword, rd
+#ifndef __ARMEB__
+		strb	\rd, [r0]
+		mov	\rd, \rd, lsr #8
+		strb	\rd, [r0]
+		mov	\rd, \rd, lsr #8
+		strb	\rd, [r0]
+		mov	\rd, \rd, lsr #8
+		strb	\rd, [r0]
+#else
+		mov	lr, \rd, lsr #24
+		strb	lr, [r0]
+		mov	lr, \rd, lsr #16
+		strb	lr, [r0]
+		mov	lr, \rd, lsr #8
+		strb	lr, [r0]
+		strb	\rd, [r0]
+#endif
+		.endm
 
 .outsb_align:	rsb	ip, ip, #4
 		cmp	ip, r2
@@ -30,86 +49,37 @@ ENTRY(__raw_writesb)
 		ands	ip, r1, #3
 		bne	.outsb_align
 
-.outsb_aligned:	stmfd	sp!, {r4 - r6, lr}
+.outsb_aligned:	stmfd	sp!, {r4, r5, lr}
 
 		subs	r2, r2, #16
 		bmi	.outsb_no_16
 
-.outsb_16_lp:	ldmia	r1!, {r3 - r6}
-
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
-
-		strb	r5, [r0]
-		mov	r5, r5, lsr #8
-		strb	r5, [r0]
-		mov	r5, r5, lsr #8
-		strb	r5, [r0]
-		mov	r5, r5, lsr #8
-		strb	r5, [r0]
-
-		strb	r6, [r0]
-		mov	r6, r6, lsr #8
-		strb	r6, [r0]
-		mov	r6, r6, lsr #8
-		strb	r6, [r0]
-		mov	r6, r6, lsr #8
-		strb	r6, [r0]
-
+.outsb_16_lp:	ldmia	r1!, {r3, r4, r5, ip}
+		outword	r3
+		outword	r4
+		outword	r5
+		outword	ip
 		subs	r2, r2, #16
 		bpl	.outsb_16_lp
 
 		tst	r2, #15
-		LOADREGS(eqfd, sp!, {r4 - r6, pc})
+		LOADREGS(eqfd, sp!, {r4, r5, pc})
 
 .outsb_no_16:	tst	r2, #8
 		beq	.outsb_no_8
 
 		ldmia	r1!, {r3, r4}
-
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
-		mov	r4, r4, lsr #8
-		strb	r4, [r0]
+		outword	r3
+		outword	r4
 
 .outsb_no_8:	tst	r2, #4
 		beq	.outsb_no_4
 
 		ldr	r3, [r1], #4
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
-		mov	r3, r3, lsr #8
-		strb	r3, [r0]
+		outword	r3
 
 .outsb_no_4:	ands	r2, r2, #3
-		LOADREGS(eqfd, sp!, {r4 - r6, pc})
+		LOADREGS(eqfd, sp!, {r4, r5, pc})
 
 		cmp	r2, #2
 		ldrb	r3, [r1], #1
@@ -119,4 +89,4 @@ ENTRY(__raw_writesb)
 		ldrgtb	r3, [r1]
 		strgtb	r3, [r0]
 
-		LOADREGS(fd, sp!, {r4 - r6, pc})
+		LOADREGS(fd, sp!, {r4, r5, pc})

arch/arm/lib/io-writesl.S

@@ -17,10 +17,15 @@ ENTRY(__raw_writesl)
 		ands	ip, r1, #3
 		bne	2f
 
-1:		ldr	r3, [r1], #4
-		str	r3, [r0]
-		subs	r2, r2, #1
-		bne	1b
+		tst	r2, #1
+		ldrne	r3, [r1], #4
+		strne	r3, [r0, #0]
+1:		subs	r2, r2, #2
+		ldrcs	r3, [r1], #4
+		ldrcs	ip, [r1], #4
+		strcs	r3, [r0, #0]
+		strcs	ip, [r0, #0]
+		bcs	1b
 		mov	pc, lr
 
 2:		bic	r1, r1, #3
@@ -31,25 +36,25 @@ ENTRY(__raw_writesl)
 
 3:		mov	ip, r3, lsr #16
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #16
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #16
+		str	ip, [r0, #0]
 		bne	3b
 		mov	pc, lr
 
 4:		mov	ip, r3, lsr #24
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #8
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #8
+		str	ip, [r0, #0]
 		bne	4b
 		mov	pc, lr
 
 5:		mov	ip, r3, lsr #8
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #24
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #24
+		str	ip, [r0, #0]
 		bne	5b
 		mov	pc, lr
 

arch/arm/mach-integrator/Makefile

@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o time.o
+obj-y			:= core.o lm.o time.o
 
 obj-$(CONFIG_LEDS)	+= leds.o
 obj-$(CONFIG_PCI)	+= pci_v3.o pci.o

arch/arm/mach-integrator/core.c

@@ -34,6 +34,8 @@
 #include <asm/hardware/amba.h>
 #include <asm/hardware/amba_kmi.h>
 
+#include <asm/arch/lm.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
@@ -46,6 +48,7 @@
  * just for now).
  */
 #define VA_IC_BASE	IO_ADDRESS(INTEGRATOR_IC_BASE) 
+#define VA_SC_BASE	IO_ADDRESS(INTEGRATOR_SC_BASE)
 #define VA_CMIC_BASE	IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
 
 /*
@@ -66,7 +69,7 @@
  * f1a00000	1a000000	Debug LEDs
  * f1b00000	1b000000	GPIO
  */
- 
+
 static struct map_desc integrator_io_desc[] __initdata = {
  { IO_ADDRESS(INTEGRATOR_HDR_BASE),   INTEGRATOR_HDR_BASE,   SZ_4K,  MT_DEVICE },
  { IO_ADDRESS(INTEGRATOR_SC_BASE),    INTEGRATOR_SC_BASE,    SZ_4K,  MT_DEVICE },
@@ -89,7 +92,7 @@ static void __init integrator_map_io(void)
 	iotable_init(integrator_io_desc, ARRAY_SIZE(integrator_io_desc));
 }
 
-#define ALLPCI ( (1 << IRQ_PCIINT0) | (1 << IRQ_PCIINT1) | (1 << IRQ_PCIINT2) | (1 << IRQ_PCIINT3) ) 
+#define ALLPCI ( (1 << IRQ_PCIINT0) | (1 << IRQ_PCIINT1) | (1 << IRQ_PCIINT2) | (1 << IRQ_PCIINT3) )
 
 static void sc_mask_irq(unsigned int irq)
 {
@@ -161,6 +164,7 @@ static struct amba_device *amba_devs[] __initdata = {
 
 static int __init register_devices(void)
 {
+	unsigned long sc_dec;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -169,6 +173,28 @@ static int __init register_devices(void)
 		amba_device_register(d, &iomem_resource);
 	}
 
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		memset(lmdev, 0, sizeof(struct lm_device));
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+
 	return 0;
 }
 

arch/arm/mach-integrator/impd1.c

@@ -10,7 +10,7 @@
  *  This file provides the core support for the IM-PD1 module.
  *
  * Module / boot parameters.
- *   id=n   impd1.id=n - set the logic module position in stack to 'n'
+ *   lmid=n   impd1.lmid=n - set the logic module position in stack to 'n'
  */
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -21,17 +21,15 @@
 #include <asm/io.h>
 #include <asm/hardware/icst525.h>
 #include <asm/hardware/amba.h>
+#include <asm/arch/lm.h>
 #include <asm/arch/impd1.h>
 #include <asm/sizes.h>
 
 static int module_id;
 
-module_param_named(lmid, module_id, int, 0);
+module_param_named(lmid, module_id, int, 0444);
 MODULE_PARM_DESC(lmid, "logic module stack position");
 
-#define ROM_OFFSET	0x0fffff00
-#define ROM_SIZE	256
-
 struct impd1_module {
 	void	*base;
 };
@@ -142,17 +140,15 @@ static struct impd1_device impd1_devs[] = {
 	}
 };
 
-static int impd1_probe(struct device *dev)
+static int impd1_probe(struct lm_device *dev)
 {
-	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *res = &pdev->resource[0];
 	struct impd1_module *impd1;
 	int i, ret;
 
-	if (pdev->id != module_id)
+	if (dev->id != module_id)
 		return -EINVAL;
 
-	if (!request_mem_region(res->start, SZ_4K, "LM registers"))
+	if (!request_mem_region(dev->resource.start, SZ_4K, "LM registers"))
 		return -EBUSY;
 
 	impd1 = kmalloc(sizeof(struct impd1_module), GFP_KERNEL);
@@ -162,22 +158,22 @@ static int impd1_probe(struct device *dev)
 	}
 	memset(impd1, 0, sizeof(struct impd1_module));
 
-	impd1->base = ioremap(res->start, SZ_4K);
+	impd1->base = ioremap(dev->resource.start, SZ_4K);
 	if (!impd1->base) {
 		ret = -ENOMEM;
 		goto free_impd1;
 	}
 
-	dev_set_drvdata(dev, impd1);
+	lm_set_drvdata(dev, impd1);
 
-	printk("IM-PD1 found at 0x%08lx\n", res->start);
+	printk("IM-PD1 found at 0x%08lx\n", dev->resource.start);
 
 	for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
 		struct impd1_device *idev = impd1_devs + i;
 		struct amba_device *d;
 		unsigned long pc_base;
 
-		pc_base = res->start + idev->offset;
+		pc_base = dev->resource.start + idev->offset;
 
 		d = kmalloc(sizeof(struct amba_device), GFP_KERNEL);
 		if (!d)
@@ -186,16 +182,16 @@ static int impd1_probe(struct device *dev)
 		memset(d, 0, sizeof(struct amba_device));
 
 		snprintf(d->dev.bus_id, sizeof(d->dev.bus_id),
-			 "lm%x:%5.5lx", pdev->id, idev->offset >> 12);
+			 "lm%x:%5.5lx", dev->id, idev->offset >> 12);
 
-		d->dev.parent	= &pdev->dev;
-		d->res.start	= res->start + idev->offset;
+		d->dev.parent	= &dev->dev;
+		d->res.start	= dev->resource.start + idev->offset;
 		d->res.end	= d->res.start + SZ_4K - 1;
 		d->res.flags	= IORESOURCE_MEM;
-		d->irq		= pdev->resource[1].start;
+		d->irq		= dev->irq;
 		d->periphid	= idev->id;
 
-		ret = amba_device_register(d, res);
+		ret = amba_device_register(d, &dev->resource);
 		if (ret) {
 			printk("unable to register device %s: %d\n",
 				d->dev.bus_id, ret);
@@ -211,47 +207,44 @@ static int impd1_probe(struct device *dev)
 	if (impd1)
 		kfree(impd1);
  release_lm:
-	release_mem_region(res->start, SZ_4K);
+	release_mem_region(dev->resource.start, SZ_4K);
 	return ret;
 }
 
-static int impd1_remove(struct device *dev)
+static void impd1_remove(struct lm_device *dev)
 {
-	struct platform_device *pdev = to_platform_device(dev);
-	struct resource *res = &pdev->resource[0];
-	struct impd1_module *impd1 = dev_get_drvdata(dev);
+	struct impd1_module *impd1 = lm_get_drvdata(dev);
 	struct list_head *l, *n;
 
-	list_for_each_safe(l, n, &dev->children) {
+	list_for_each_safe(l, n, &dev->dev.children) {
 		struct device *d = list_to_dev(l);
 
 		device_unregister(d);
 	}
 
-	dev_set_drvdata(dev, NULL);
+	lm_set_drvdata(dev, NULL);
 
 	iounmap(impd1->base);
 	kfree(impd1);
-	release_mem_region(res->start, SZ_4K);
-
-	return 0;
+	release_mem_region(dev->resource.start, SZ_4K);
 }
 
-static struct device_driver impd1_driver = {
-	.name		= "lm",
-	.bus		= &platform_bus_type,
+static struct lm_driver impd1_driver = {
+	.drv = {
+		.name	= "impd1",
+	},
 	.probe		= impd1_probe,
 	.remove		= impd1_remove,
 };
 
 static int __init impd1_init(void)
 {
-	return driver_register(&impd1_driver);
+	return lm_driver_register(&impd1_driver);
 }
 
 static void __exit impd1_exit(void)
 {
-	driver_unregister(&impd1_driver);
+	lm_driver_unregister(&impd1_driver);
 }
 
 module_init(impd1_init);

arch/arm/mach-integrator/lm.c

+/*
+ *  linux/arch/arm/mach-integrator/lm.c
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/arch/lm.h>
+
+#define to_lm_device(d)	container_of(d, struct lm_device, dev)
+#define to_lm_driver(d)	container_of(d, struct lm_driver, drv)
+
+static int lm_match(struct device *dev, struct device_driver *drv)
+{
+	return 1;
+}
+
+static struct bus_type lm_bustype = {
+	.name		= "logicmodule",
+	.match		= lm_match,
+//	.suspend	= lm_suspend,
+//	.resume		= lm_resume,
+};
+
+static int __init lm_init(void)
+{
+	return bus_register(&lm_bustype);
+}
+
+postcore_initcall(lm_init);
+
+static int lm_bus_probe(struct device *dev)
+{
+	struct lm_device *lmdev = to_lm_device(dev);
+	struct lm_driver *lmdrv = to_lm_driver(dev->driver);
+
+	return lmdrv->probe(lmdev);
+}
+
+static int lm_bus_remove(struct device *dev)
+{
+	struct lm_device *lmdev = to_lm_device(dev);
+	struct lm_driver *lmdrv = to_lm_driver(dev->driver);
+
+	lmdrv->remove(lmdev);
+	return 0;
+}
+
+int lm_driver_register(struct lm_driver *drv)
+{
+	drv->drv.bus = &lm_bustype;
+	drv->drv.probe = lm_bus_probe;
+	drv->drv.remove = lm_bus_remove;
+
+	return driver_register(&drv->drv);
+}
+
+void lm_driver_unregister(struct lm_driver *drv)
+{
+	driver_unregister(&drv->drv);
+}
+
+static void lm_device_release(struct device *dev)
+{
+	struct lm_device *d = to_lm_device(dev);
+
+	kfree(d);
+}
+
+int lm_device_register(struct lm_device *dev)
+{
+	int ret;
+
+	dev->dev.release = lm_device_release;
+	dev->dev.bus = &lm_bustype;
+
+	snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id), "lm%d", dev->id);
+	dev->resource.name = dev->dev.bus_id;
+
+	ret = request_resource(&iomem_resource, &dev->resource);
+	if (ret == 0) {
+		ret = device_register(&dev->dev);
+		if (ret)
+			release_resource(&dev->resource);
+	}
+	return ret;
+}

arch/arm/mm/Kconfig

+comment "Processor Type"
+
+config CPU_32
+	bool
+	default y
+
+# Select CPU types depending on the architecture selected.  This selects
+# which CPUs we support in the kernel image, and the compiler instruction
+# optimiser behaviour.
+
+# ARM610
+config CPU_ARM610
+	bool "Support ARM610 processor"
+	depends on ARCH_RPC
+	select CPU_32v3
+	select CPU_CACHE_V3
+	select CPU_COPY_V3
+	select CPU_TLB_V3
+	help
+	  The ARM610 is the successor to the ARM3 processor
+	  and was produced by VLSI Technology Inc.
+
+	  Say Y if you want support for the ARM610 processor.
+	  Otherwise, say N.
+
+# ARM710
+config CPU_ARM710
+	bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
+	default y if ARCH_CLPS7500
+	select CPU_32v3
+	select CPU_CACHE_V3
+	select CPU_COPY_V3
+	select CPU_TLB_V3
+	help
+	  A 32-bit RISC microprocessor based on the ARM7 processor core
+	  designed by Advanced RISC Machines Ltd. The ARM710 is the
+	  successor to the ARM610 processor. It was released in
+	  July 1994 by VLSI Technology Inc.
+
+	  Say Y if you want support for the ARM710 processor.
+	  Otherwise, say N.
+
+# ARM720T
+config CPU_ARM720T
+	bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
+	default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712
+	select CPU_32v4
+	select CPU_ABRT_LV4T
+	select CPU_CACHE_V4
+	select CPU_COPY_V4WT
+	select CPU_TLB_V4WT
+	help
+	  A 32-bit RISC processor with 8kByte Cache, Write Buffer and
+	  MMU built around an ARM7TDMI core.
+
+	  Say Y if you want support for the ARM720T processor.
+	  Otherwise, say N.
+
+# ARM920T
+config CPU_ARM920T
+	bool "Support ARM920T processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v4
+	select CPU_ABRT_EV4T
+	select CPU_CACHE_V4WT
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WBI
+	help
+	  The ARM920T is licensed to be produced by numerous vendors,
+	  and is used in the Maverick EP9312.  More information at
+	  <http://linuxdevices.com/products/PD2382866068.html>.
+
+	  Say Y if you want support for the ARM920T processor.
+	  Otherwise, say N.
+
+# ARM922T
+config CPU_ARM922T
+	bool
+	depends on ARCH_CAMELOT
+	default y
+	select CPU_32v4
+	select CPU_ABRT_EV4T
+	select CPU_CACHE_V4WT
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WBI
+	help
+	  The ARM922T is a version of the ARM920T, but with smaller
+	  instruction and data caches. It is used in Altera's
+	  Excalibur XA device family.
+
+	  Say Y if you want support for the ARM922T processor.
+	  Otherwise, say N.
+
+# ARM926T
+config CPU_ARM926T
+	bool "Support ARM926T processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v5
+	select CPU_ABRT_EV5TJ
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WBI
+	help
+	  This is a variant of the ARM920.  It has slightly different
+	  instruction sequences for cache and TLB operations.  Curiously,
+	  there is no documentation on it at the ARM corporate website.
+
+	  Say Y if you want support for the ARM926T processor.
+	  Otherwise, say N.
+
+# ARM1020 - needs validating
+config CPU_ARM1020
+	bool "Support ARM1020T (rev 0) processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v5
+	select CPU_ABRT_EV4T
+	select CPU_CACHE_V4WT
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WBI
+	help
+	  The ARM1020 is the 32K cached version of the ARM10 processor,
+	  with an addition of a floating-point unit.
+
+	  Say Y if you want support for the ARM1020 processor.
+	  Otherwise, say N.
+
+# ARM1020E - needs validating
+config CPU_ARM1020E
+	bool "Support ARM1020E processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v5
+	select CPU_ABRT_EV4T
+	select CPU_CACHE_V4WT
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WBI
+	depends on n
+
+# ARM1022E
+config CPU_ARM1022
+	bool "Support ARM1022E processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v5
+	select CPU_ABRT_EV4T
+	select CPU_COPY_V4WB # can probably do better
+	select CPU_TLB_V4WBI
+	help
+	  The ARM1022E is an implementation of the ARMv5TE architecture
+	  based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
+	  embedded trace macrocell, and a floating-point unit.
+
+	  Say Y if you want support for the ARM1022E processor.
+	  Otherwise, say N.
+
+# ARM1026EJ-S
+config CPU_ARM1026
+	bool "Support ARM1026EJ-S processor"
+	depends on ARCH_INTEGRATOR
+	select CPU_32v5
+	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+	select CPU_COPY_V4WB # can probably do better
+	select CPU_TLB_V4WBI
+	help
+	  The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
+	  based upon the ARM10 integer core.
+
+	  Say Y if you want support for the ARM1026EJ-S processor.
+	  Otherwise, say N.
+
+# SA110
+config CPU_SA110
+	bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && !ARCH_ANAKIN && ARCH_RPC
+	default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI || ARCH_ANAKIN
+	select CPU_32v3 if ARCH_RPC
+	select CPU_32v4 if !ARCH_RPC
+	select CPU_ABRT_EV4
+	select CPU_CACHE_V4WB
+	select CPU_COPY_V4WB
+	select CPU_TLB_V4WB
+	help
+	  The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
+	  is available at five speeds ranging from 100 MHz to 233 MHz.
+	  More information is available at
+	  <http://developer.intel.com/design/strong/sa110.htm>.
+
+	  Say Y if you want support for the SA-110 processor.
+	  Otherwise, say N.
+
+# SA1100
+config CPU_SA1100
+	bool
+	depends on ARCH_SA1100
+	default y
+	select CPU_32v4
+	select CPU_ABRT_EV4
+	select CPU_CACHE_V4WB
+	select CPU_TLB_V4WB
+	select CPU_MINICACHE
+
+# XScale
+config CPU_XSCALE
+	bool
+	depends on ARCH_IOP3XX || ARCH_ADIFCC || ARCH_PXA
+	default y
+	select CPU_32v5
+	select CPU_ABRT_EV5T
+	select CPU_TLB_V4WBI
+	select CPU_MINICACHE
+
+# This defines the compiler instruction set which depends on the machine type.
+config CPU_32v3
+	bool
+
+config CPU_32v4
+	bool
+
+config CPU_32v5
+	bool
+
+# The abort model
+config CPU_ABRT_EV4
+	bool
+
+config CPU_ABRT_EV4T
+	bool
+
+config CPU_ABRT_LV4T
+	bool
+
+config CPU_ABRT_EV5T
+	bool
+
+config CPU_ABRT_EV5TJ
+	bool
+
+# The cache model
+config CPU_CACHE_V3
+	bool
+
+config CPU_CACHE_V4
+	bool
+
+config CPU_CACHE_V4WT
+	bool
+
+config CPU_CACHE_V4WB
+	bool
+
+# The copy-page model
+config CPU_COPY_V3
+	bool
+
+config CPU_COPY_V4WT
+	bool
+
+config CPU_COPY_V4WB
+	bool
+
+# This selects the TLB model
+config CPU_TLB_V3
+	bool
+	help
+	  ARM Architecture Version 3 TLB.
+
+config CPU_TLB_V4WT
+	bool
+	help
+	  ARM Architecture Version 4 TLB with writethrough cache.
+
+config CPU_TLB_V4WB
+	bool
+	help
+	  ARM Architecture Version 4 TLB with writeback cache.
+
+config CPU_TLB_V4WBI
+	bool
+	help
+	  ARM Architecture Version 4 TLB with writeback cache and invalidate
+	  instruction cache entry.
+
+config CPU_TLB_V6
+	bool
+
+config CPU_MINICACHE
+	bool
+	help
+	  Processor has a minicache.
+
+comment "Processor Features"
+
+config ARM_THUMB
+	bool "Support Thumb user binaries"
+	depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE
+	default y
+	help
+	  Say Y if you want to have kernel support for ARM Thumb instructions,
+	  fault handlers, and system calls.
+
+	  The Thumb instruction set is a compressed form of the standard ARM
+	  instruction set resulting in smaller binaries at the expense of
+	  slightly less efficient code.
+
+	  If you don't know what this all is, saying Y is a safe choice.
+
+config CPU_BIG_ENDIAN
+	bool "Build big-endian kernel"
+	depends on ARCH_SUPPORTS_BIG_ENDIAN
+	help
+	  Say Y if you plan on running a kernel in big-endian mode.
+	  Note that your board must be properly built and your board
+	  port must properly enable and big-endian related features
+	  of your chipset/board/processor.
+
+config CPU_ICACHE_DISABLE
+	bool "Disable I-Cache"
+	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020
+	help
+	  Say Y here to disable the processor instruction cache. Unless
+	  you have a reason not to or are unsure, say N.
+
+config CPU_DCACHE_DISABLE
+	bool "Disable D-Cache"
+	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020
+	help
+	  Say Y here to disable the processor data cache. Unless
+	  you have a reason not to or are unsure, say N.
+
+config CPU_DCACHE_WRITETHROUGH
+	bool "Force write through D-cache"
+	depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
+	help
+	  Say Y here to use the data cache in writethough mode. Unless you
+	  specifically require this or are unsure, say N.
+
+config CPU_CACHE_ROUND_ROBIN
+	bool "Round robin I and D cache replacement algorithm"
+	depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
+	help
+	  Say Y here to use the predictable round-robin cache replacement
+	  policy.  Unless you specifically require this or are unsure, say N.
+
+config CPU_BPREDICT_DISABLE
+	bool "Disable branch prediction"
+	depends on CPU_ARM1020
+	help
+	  Say Y here to disable branch prediction.  If unsure, say N.

arch/arm/mm/Makefile

@@ -2,29 +2,48 @@
 # Makefile for the linux arm-specific parts of the memory manager.
 #
 
-# Object file lists.
+obj-y				:= consistent.o extable.o fault-armv.o \
+				   fault-common.o init.o ioremap.o mm-armv.o
 
-obj-y		:= consistent.o extable.o fault-armv.o fault-common.o \
-		   init.o ioremap.o mm-armv.o
-obj-$(CONFIG_MODULES) += proc-syms.o
+obj-$(CONFIG_MODULES)		+= proc-syms.o
 
-obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
-obj-$(CONFIG_DISCONTIGMEM) += discontig.o
+obj-$(CONFIG_ALIGNMENT_TRAP)	+= alignment.o
+obj-$(CONFIG_DISCONTIGMEM)	+= discontig.o
 
-# ARMv3
-p-$(CONFIG_CPU_ARM610)	+= proc-arm6_7.o  tlb-v3.o    cache-v3.o    copypage-v3.o
-p-$(CONFIG_CPU_ARM710)	+= proc-arm6_7.o  tlb-v3.o    cache-v3.o    copypage-v3.o
+obj-$(CONFIG_CPU_ABRT_EV4)	+= abort-ev4.o
+obj-$(CONFIG_CPU_ABRT_EV4T)	+= abort-ev4t.o
+obj-$(CONFIG_CPU_ABRT_LV4T)	+= abort-lv4t.o
+obj-$(CONFIG_CPU_ABRT_EV5T)	+= abort-ev5t.o
+obj-$(CONFIG_CPU_ABRT_EV5TJ)	+= abort-ev5tj.o
 
-# ARMv4
-p-$(CONFIG_CPU_ARM720T)	+= proc-arm720.o  tlb-v4.o    cache-v4.o    copypage-v4wt.o abort-lv4t.o
-p-$(CONFIG_CPU_ARM920T)	+= proc-arm920.o  tlb-v4wbi.o cache-v4wt.o  copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_ARM922T)	+= proc-arm922.o  tlb-v4wbi.o cache-v4wt.o  copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_ARM1020)	+= proc-arm1020.o tlb-v4wbi.o cache-v4wt.o  copypage-v4wb.o abort-ev4t.o
-p-$(CONFIG_CPU_SA110)	+= proc-sa110.o   tlb-v4wb.o  cache-v4wb.o  copypage-v4wb.o abort-ev4.o
-p-$(CONFIG_CPU_SA1100)	+= proc-sa1100.o  tlb-v4wb.o  cache-v4wb.o  copypage-v4mc.o abort-ev4.o   minicache.o
+obj-$(CONFIG_CPU_CACHE_V3)	+= cache-v3.o
+obj-$(CONFIG_CPU_CACHE_V4)	+= cache-v4.o
+obj-$(CONFIG_CPU_CACHE_V4WT)	+= cache-v4wt.o
+obj-$(CONFIG_CPU_CACHE_V4WB)	+= cache-v4wb.o
 
-# ARMv5
-p-$(CONFIG_CPU_ARM926T)	+= proc-arm926.o  tlb-v4wbi.o copypage-v4wb.o abort-ev5tej.o
-p-$(CONFIG_CPU_XSCALE)	+= proc-xscale.o  tlb-v4wbi.o copypage-xscale.o abort-xscale.o minicache.o
+obj-$(CONFIG_CPU_COPY_V3)	+= copypage-v3.o
+obj-$(CONFIG_CPU_COPY_V4WT)	+= copypage-v4wt.o
+obj-$(CONFIG_CPU_COPY_V4WB)	+= copypage-v4wb.o
+obj-$(CONFIG_CPU_SA1100)	+= copypage-v4mc.o
+obj-$(CONFIG_CPU_XSCALE)	+= copypage-xscale.o
 
-obj-y		+= $(sort $(p-y))
+obj-$(CONFIG_CPU_MINICACHE)	+= minicache.o
+
+obj-$(CONFIG_CPU_TLB_V3)	+= tlb-v3.o
+obj-$(CONFIG_CPU_TLB_V4WT)	+= tlb-v4.o
+obj-$(CONFIG_CPU_TLB_V4WB)	+= tlb-v4wb.o
+obj-$(CONFIG_CPU_TLB_V4WBI)	+= tlb-v4wbi.o
+
+obj-$(CONFIG_CPU_ARM610)	+= proc-arm6_7.o
+obj-$(CONFIG_CPU_ARM710)	+= proc-arm6_7.o
+obj-$(CONFIG_CPU_ARM720T)	+= proc-arm720.o
+obj-$(CONFIG_CPU_ARM920T)	+= proc-arm920.o
+obj-$(CONFIG_CPU_ARM922T)	+= proc-arm922.o
+obj-$(CONFIG_CPU_ARM926T)	+= proc-arm926.o
+obj-$(CONFIG_CPU_ARM1020)	+= proc-arm1020.o
+obj-$(CONFIG_CPU_ARM1020E)	+= proc-arm1020e.o
+obj-$(CONFIG_CPU_ARM1022)	+= proc-arm1022.o
+obj-$(CONFIG_CPU_ARM1026)	+= proc-arm1026.o
+obj-$(CONFIG_CPU_SA110)		+= proc-sa110.o
+obj-$(CONFIG_CPU_SA1100)	+= proc-sa1100.o
+obj-$(CONFIG_CPU_XSCALE)	+= proc-xscale.o

arch/arm/mm/abort-xscale.S → arch/arm/mm/abort-ev5t.S

 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: xscale_abort
+ * Function: v5t_early_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -16,12 +16,9 @@
  * Note: we read user space.  This means we might cause a data
  * abort here if the I-TLB and D-TLB aren't seeing the same
  * picture.  Unfortunately, this does happen.  We live with it.
- *
- * Note: Xscale is contains non-standard architecture extensions.
- * It requires its own early abort handler
  */
 	.align	5
-ENTRY(xscale_abort)
+ENTRY(v5t_early_abort)
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	tst	r3, #PSR_T_BIT

arch/arm/mm/abort-ev5tej.S → arch/arm/mm/abort-ev5tj.S

 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: v5tej_early_abort
+ * Function: v5tj_early_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -18,19 +18,19 @@
  * picture.  Unfortunately, this does happen.  We live with it.
  */
 	.align	5
-ENTRY(v5tej_early_abort)
+ENTRY(v5tj_early_abort)
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR
-	tst	r3, #PSR_J_BIT
+	tst	r3, #PSR_J_BIT			@ Java?
 	orrne	r1, r1, #1 << 11		@ always assume write
-	bne	1f
-	tst	r3, #PSR_T_BIT
+	movne	pc, lr
+	tst	r3, #PSR_T_BIT			@ Thumb?
 	ldrneh	r3, [r2]			@ read aborted thumb instruction
 	ldreq	r3, [r2]			@ read aborted ARM instruction
 	movne	r3, r3, lsl #(21 - 12)		@ move thumb bit 11 to ARM bit 20
-	tst	r3, #1 << 20			@ L = 1 -> write
+	tst	r3, #1 << 20			@ L = 0 -> write
 	orreq	r1, r1, #1 << 11		@ yes.
-1:	mov	pc, lr
+	mov	pc, lr
 
 

arch/arm/mm/cache-v3.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -107,6 +108,9 @@ ENTRY(v3_dma_flush_range)
 ENTRY(v3_dma_clean_range)
 	mov	pc, lr
 
+	__INITDATA
+
+	.type	v3_cache_fns, #object
 ENTRY(v3_cache_fns)
 	.long	v3_flush_kern_cache_all
 	.long	v3_flush_user_cache_all
@@ -116,3 +120,4 @@ ENTRY(v3_cache_fns)
 	.long	v3_dma_inv_range
 	.long	v3_dma_clean_range
 	.long	v3_dma_flush_range
+	.size	v3_cache_fns, . - v3_cache_fns

arch/arm/mm/cache-v4.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -109,6 +110,9 @@ ENTRY(v4_dma_flush_range)
 ENTRY(v4_dma_clean_range)
 	mov	pc, lr
 
+	__INITDATA
+
+	.type	v4_cache_fns, #object
 ENTRY(v4_cache_fns)
 	.long	v4_flush_kern_cache_all
 	.long	v4_flush_user_cache_all
@@ -118,3 +122,4 @@ ENTRY(v4_cache_fns)
 	.long	v4_dma_inv_range
 	.long	v4_dma_clean_range
 	.long	v4_dma_flush_range
+	.size	v4_cache_fns, . - v4_cache_fns

arch/arm/mm/cache-v4wb.S

@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -185,6 +186,9 @@ ENTRY(v4wb_dma_clean_range)
 	.globl	v4wb_dma_flush_range
 	.set	v4wb_dma_flush_range, v4wb_coherent_kern_range
 
+	__INITDATA
+
+	.type	v4wb_cache_fns, #object
 ENTRY(v4wb_cache_fns)
 	.long	v4wb_flush_kern_cache_all
 	.long	v4wb_flush_user_cache_all
@@ -194,3 +198,4 @@ ENTRY(v4wb_cache_fns)
 	.long	v4wb_dma_inv_range
 	.long	v4wb_dma_clean_range
 	.long	v4wb_dma_flush_range
+	.size	v4wb_cache_fns, . - v4wb_cache_fns

arch/arm/mm/cache-v4wt.S

@@ -12,6 +12,7 @@
  *  We assume that the write buffer is not enabled.
  */
 #include <linux/linkage.h>
+#include <linux/init.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
 #include "proc-macros.S"
@@ -158,6 +159,9 @@ ENTRY(v4wt_dma_clean_range)
 	.globl	v4wt_dma_flush_range
 	.equ	v4wt_dma_flush_range, v4wt_dma_inv_range
 
+	__INITDATA
+
+	.type	v4wt_cache_fns, #object
 ENTRY(v4wt_cache_fns)
 	.long	v4wt_flush_kern_cache_all
 	.long	v4wt_flush_user_cache_all
@@ -167,4 +171,4 @@ ENTRY(v4wt_cache_fns)
 	.long	v4wt_dma_inv_range
 	.long	v4wt_dma_clean_range
 	.long	v4wt_dma_flush_range
-
+	.size	v4wt_cache_fns, . - v4wt_cache_fns

arch/arm/mm/copypage-v3.S

@@ -58,8 +58,10 @@ ENTRY(v3_clear_user_page)
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v3_user_fns, #object
 ENTRY(v3_user_fns)
 	.long	v3_clear_user_page
 	.long	v3_copy_user_page
+	.size	v3_user_fns, . - v3_user_fns

arch/arm/mm/copypage-v4mc.S

@@ -71,9 +71,10 @@ ENTRY(v4_mc_clear_user_page)
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4_mc_user_fns, #object
 ENTRY(v4_mc_user_fns)
 	.long	v4_mc_clear_user_page
 	.long	v4_mc_copy_user_page
-
+	.size	v4_mc_user_fns, . - v4_mc_user_fns

arch/arm/mm/copypage-v4wb.S

@@ -70,9 +70,10 @@ ENTRY(v4wb_clear_user_page)
 	mcr	p15, 0, r1, c7, c10, 4		@ 1   drain WB
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4wb_user_fns, #object
 ENTRY(v4wb_user_fns)
 	.long	v4wb_clear_user_page
 	.long	v4wb_copy_user_page
-
+	.size	v4wb_user_fns, . - v4wb_user_fns

arch/arm/mm/copypage-v4wt.S

@@ -64,9 +64,10 @@ ENTRY(v4wt_clear_user_page)
 	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache
 	ldr	pc, [sp], #4
 
-	__INIT
+	__INITDATA
 
+	.type	v4wt_user_fns, #object
 ENTRY(v4wt_user_fns)
 	.long	v4wt_clear_user_page
 	.long	v4wt_copy_user_page
-
+	.size	v4wt_user_fns, . - v4wt_user_fns

arch/arm/mm/copypage-xscale.S

@@ -104,8 +104,10 @@ ENTRY(xscale_mc_clear_user_page)
 	bne	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
+	.type	xscale_mc_user_fns, #object
 ENTRY(xscale_mc_user_fns)
 	.long	xscale_mc_clear_user_page
 	.long	xscale_mc_copy_user_page
+	.size	xscale_mc_user_fns, . - xscale_mc_user_fns

arch/arm/mm/fault-armv.c

@@ -14,9 +14,11 @@
 #include <linux/ptrace.h>
 #include <linux/mm.h>
 #include <linux/bitops.h>
+#include <linux/vmalloc.h>
 #include <linux/init.h>
 
 #include <asm/cacheflush.h>
+#include <asm/io.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
@@ -127,6 +129,8 @@ do_PrefetchAbort(unsigned long addr, struct pt_regs *regs)
 	do_translation_fault(addr, 0, regs);
 }
 
+static unsigned long shared_pte_mask = L_PTE_CACHEABLE;
+
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -157,9 +161,9 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
 	 * If this page isn't present, or is already setup to
 	 * fault (ie, is old), we can safely ignore any issues.
 	 */
-	if (pte_present(entry) && pte_val(entry) & L_PTE_CACHEABLE) {
+	if (pte_present(entry) && pte_val(entry) & shared_pte_mask) {
 		flush_cache_page(vma, address);
-		pte_val(entry) &= ~L_PTE_CACHEABLE;
+		pte_val(entry) &= ~shared_pte_mask;
 		set_pte(pte, entry);
 		flush_tlb_page(vma, address);
 		ret = 1;
@@ -297,3 +301,65 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 		make_coherent(vma, addr, page, dirty);
 	}
 }
+
+/*
+ * Check whether the write buffer has physical address aliasing
+ * issues.  If it has, we need to avoid them for the case where
+ * we have several shared mappings of the same object in user
+ * space.
+ */
+static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
+{
+	register unsigned long zero = 0, one = 1, val;
+
+	local_irq_disable();
+	mb();
+	*p1 = one;
+	mb();
+	*p2 = zero;
+	mb();
+	val = *p1;
+	mb();
+	local_irq_enable();
+	return val != zero;
+}
+
+void __init check_writebuffer_bugs(void)
+{
+	struct page *page;
+	const char *reason;
+	unsigned long v = 1;
+
+	printk(KERN_INFO "CPU: Testing write buffer coherency: ");
+
+	page = alloc_page(GFP_KERNEL);
+	if (page) {
+		unsigned long *p1, *p2;
+		pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
+					 L_PTE_DIRTY|L_PTE_WRITE|
+					 L_PTE_BUFFERABLE);
+
+		p1 = vmap(&page, 1, VM_IOREMAP, prot);
+		p2 = vmap(&page, 1, VM_IOREMAP, prot);
+
+		if (p1 && p2) {
+			v = check_writebuffer(p1, p2);
+			reason = "enabling work-around";
+		} else {
+			reason = "unable to map memory\n";
+		}
+
+		vunmap(p1);
+		vunmap(p2);
+		put_page(page);
+	} else {
+		reason = "unable to grab page\n";
+	}
+
+	if (v) {
+		printk("failed, %s\n", reason);
+		shared_pte_mask |= L_PTE_BUFFERABLE;
+	} else {
+		printk("ok\n");
+	}
+}

arch/arm/mm/mm-armv.c

@@ -392,12 +392,19 @@ static void __init create_mapping(struct map_desc *md)
 	long off;
 
 	if (md->virtual != vectors_base() && md->virtual < PAGE_OFFSET) {
-		printk(KERN_WARNING "MM: not creating mapping for "
+		printk(KERN_WARNING "BUG: not creating mapping for "
 		       "0x%08lx at 0x%08lx in user region\n",
 		       md->physical, md->virtual);
 		return;
 	}
 
+	if (md->type == MT_DEVICE &&
+	    md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
+		printk(KERN_WARNING "BUG: mapping for 0x%08lx at 0x%08lx "
+		       "overlaps vmalloc space\n",
+		       md->physical, md->virtual);
+	}
+
 	domain	  = mem_types[md->type].domain;
 	prot_pte  = __pgprot(mem_types[md->type].prot_pte);
 	prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
@@ -409,7 +416,7 @@ static void __init create_mapping(struct map_desc *md)
 
 	if (mem_types[md->type].prot_l1 == 0 &&
 	    (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
-		printk(KERN_WARNING "MM: map for 0x%08lx at 0x%08lx can not "
+		printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 		       "be mapped using pages, ignoring.\n",
 		       md->physical, md->virtual);
 		return;

arch/arm/mm/proc-arm1020.S

 /*
- *  linux/arch/arm/mm/arm1020.S: MMU functions for ARM1020
+ *  linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
  *
  *  Copyright (C) 2000 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/constants.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include <asm/hardware.h>
@@ -379,19 +380,19 @@ ENTRY(cpu_arm1020_switch_mm)
 ENTRY(cpu_arm1020_set_pte)
 	str	r1, [r0], #-2048		@ linux version
 
-	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
-	orr	r2, r2, #HPTE_TYPE_SMALL
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
+	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #LPTE_USER			@ User?
-	orrne	r2, r2, #HPTE_AP_READ
+	tst	r1, #L_PTE_USER			@ User?
+	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-	orreq	r2, r2, #HPTE_AP_WRITE
+	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
 	movne	r2, #0
 
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -408,31 +409,9 @@ ENTRY(cpu_arm1020_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm1020_name)
-	.ascii	"Arm1020"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-#ifndef CONFIG_CPU_BPREDICT_DISABLE
-	.ascii	"B"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm1020_setup, #function
 __arm1020_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -445,10 +424,8 @@ __arm1020_setup:
 /*
  * Clear out 'unwanted' bits (then put them in if we need them)
  */
-	bic	r0, r0, #0x0e00 		@ ....??r.........
-	bic	r0, r0, #0x0002 		@ ..............a.
-	bic	r0, r0, #0x000c 		@ W,D
-	bic	r0, r0, #0x1000 		@ I
+	bic	r0, r0, #0x1e00 		@ i...??r.........
+	bic	r0, r0, #0x000e 		@ ............wca.
 /*
  * Turn on what we want
  */
@@ -468,8 +445,9 @@ __arm1020_setup:
 	orr	r0, r0, #0x1000 		@ I Cache on
 #endif
 	mov	pc, lr
+	.size	__arm1020_setup, . - __arm1020_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -485,26 +463,51 @@ arm1020_processor_functions:
 	.word	cpu_arm1020_dcache_clean_area
 	.word	cpu_arm1020_switch_mm
 	.word	cpu_arm1020_set_pte
-
 	.size	arm1020_processor_functions, . - arm1020_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
-	.asciz	"armv4t"
+	.asciz	"armv5t"
 	.size	cpu_arch_name, . - cpu_arch_name
 
 	.type	cpu_elf_name, #object
 cpu_elf_name:
-	.asciz	"v4"
+	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm1020_name, #object
+cpu_arm1020_name:
+	.ascii	"ARM1020"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+#ifndef CONFIG_CPU_BPREDICT_DISABLE
+	.ascii	"B"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+	.ascii	"\0"
+	.size	cpu_arm1020_name, . - cpu_arm1020_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr
 
 	.type	__arm1020_proc_info,#object
 __arm1020_proc_info:
-	.long	0x4100a200
-	.long	0xff00fff0
+	.long	0x4104a200			@ ARM 1020T (Architecture v5T)
+	.long	0xff0ffff0
 	.long	0x00000c02			@ mmuflags
 	b	__arm1020_setup
 	.long	cpu_arch_name

arch/arm/mm/proc-arm6_7.S

@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/constants.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
 
@@ -214,19 +215,19 @@ ENTRY(cpu_arm6_set_pte)
 ENTRY(cpu_arm7_set_pte)
 		str	r1, [r0], #-2048		@ linux version
 
-		eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+		eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-		bic	r2, r1, #0xff0
-		bic	r2, r2, #3
-		orr	r2, r2, #HPTE_TYPE_SMALL
+		bic	r2, r1, #PTE_SMALL_AP_MASK
+		bic	r2, r2, #PTE_TYPE_MASK
+		orr	r2, r2, #PTE_TYPE_SMALL
 
-		tst	r1, #LPTE_USER | LPTE_EXEC	@ User or Exec?
-		orrne	r2, r2, #HPTE_AP_READ
+		tst	r1, #L_PTE_USER			@ User?
+		orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-		tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-		orreq	r2, r2, #HPTE_AP_WRITE
+		tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+		orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-		tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young
+		tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young
 		movne	r2, #0
 
 		str	r2, [r0]			@ hardware version
@@ -246,16 +247,9 @@ ENTRY(cpu_arm7_reset)
 		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
 		mov	pc, r0
 
-cpu_arm6_name:	.asciz	"ARM6"
-cpu_arm610_name:
-		.asciz	"ARM610"
-cpu_arm7_name:	.asciz	"ARM7"
-cpu_arm710_name:
-		.asciz	"ARM710"
-		.align
-
 		__INIT
 
+		.type	__arm6_setup, #function
 __arm6_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
@@ -265,7 +259,9 @@ __arm6_setup:	mov	r0, #0
 		mov	r0, #0x3d			@ . ..RS BLDP WCAM
 		orr	r0, r0, #0x100			@ . ..01 0011 1101
 		mov	pc, lr
+		.size	__arm6_setup, . - __arm6_setup
 
+		.type	__arm7_setup, #function
 __arm7_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
 		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
@@ -275,6 +271,9 @@ __arm7_setup:	mov	r0, #0
 		mov	r0, #0x7d			@ . ..RS BLDP WCAM
 		orr	r0, r0, #0x100			@ . ..01 0111 1101
 		mov	pc, lr
+		.size	__arm7_setup, . - __arm7_setup
+
+		__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -308,6 +307,8 @@ ENTRY(arm7_processor_functions)
 		.word	cpu_arm7_set_pte
 		.size	arm7_processor_functions, . - arm7_processor_functions
 
+		.section ".rodata"
+
 		.type	cpu_arch_name, #object
 cpu_arch_name:	.asciz	"armv3"
 		.size	cpu_arch_name, . - cpu_arch_name
@@ -315,6 +316,25 @@ cpu_arch_name:	.asciz	"armv3"
 		.type	cpu_elf_name, #object
 cpu_elf_name:	.asciz	"v3"
 		.size	cpu_elf_name, . - cpu_elf_name
+
+		.type	cpu_arm6_name, #object
+cpu_arm6_name:	.asciz	"ARM6"
+		.size	cpu_arm6_name, . - cpu_arm6_name
+
+		.type	cpu_arm610_name, #object
+cpu_arm610_name:
+		.asciz	"ARM610"
+		.size	cpu_arm610_name, . - cpu_arm610_name
+
+		.type	cpu_arm7_name, #object
+cpu_arm7_name:	.asciz	"ARM7"
+		.size	cpu_arm7_name, . - cpu_arm7_name
+
+		.type	cpu_arm710_name, #object
+cpu_arm710_name:
+		.asciz	"ARM710"
+		.size	cpu_arm710_name, . - cpu_arm710_name
+
 		.align
 
 		.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm720.S

@@ -34,6 +34,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/constants.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
 #include <asm/hardware.h>
@@ -90,19 +91,19 @@ ENTRY(cpu_arm720_switch_mm)
 ENTRY(cpu_arm720_set_pte)
 		str	r1, [r0], #-2048		@ linux version
 
-		eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+		eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-		bic	r2, r1, #0xff0
-		bic	r2, r2, #3
-		orr	r2, r2, #HPTE_TYPE_SMALL
+		bic	r2, r1, #PTE_SMALL_AP_MASK
+		bic	r2, r2, #PTE_TYPE_MASK
+		orr	r2, r2, #PTE_TYPE_SMALL
 
-		tst	r1, #LPTE_USER			@ User?
-		orrne	r2, r2, #HPTE_AP_READ
+		tst	r1, #L_PTE_USER			@ User?
+		orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-		tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-		orreq	r2, r2, #HPTE_AP_WRITE
+		tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+		orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-		tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young
+		tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young
 		movne	r2, #0
 
 		str	r2, [r0]			@ hardware version
@@ -123,13 +124,9 @@ ENTRY(cpu_arm720_reset)
 		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
 		mov	pc, r0
 
-	
-cpu_arm720_name:
-		.asciz	"ARM720T"
-		.align
-
 		__INIT
 
+		.type	__arm720_setup, #function
 __arm720_setup:	mov	r0, #0
 		mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
 		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
@@ -142,6 +139,9 @@ __arm720_setup:	mov	r0, #0
 		orr	r0, r0, #0x2100			@ .... .... .111 .... (old)
 		orr	r0, r0, #0x003d			@ ..1. ..01 ..11 1101 (new)
 		mov	pc, lr				@ __ret (head-armv.S)
+		.size	__arm720_setup, . - __arm720_setup
+
+		__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -159,6 +159,8 @@ ENTRY(arm720_processor_functions)
 		.word	cpu_arm720_set_pte
 		.size	arm720_processor_functions, . - arm720_processor_functions
 
+		.section ".rodata"
+
 		.type	cpu_arch_name, #object
 cpu_arch_name:	.asciz	"armv4t"
 		.size	cpu_arch_name, . - cpu_arch_name
@@ -166,6 +168,12 @@ cpu_arch_name:	.asciz	"armv4t"
 		.type	cpu_elf_name, #object
 cpu_elf_name:	.asciz	"v4"
 		.size	cpu_elf_name, . - cpu_elf_name
+
+		.type	cpu_arm720_name, #object
+cpu_arm720_name:
+		.asciz	"ARM720T"
+		.size	cpu_arm720_name, . - cpu_arm720_name
+
 		.align
 
 /*

arch/arm/mm/proc-arm920.S

 /*
- *  linux/arch/arm/mm/arm920.S: MMU functions for ARM920
+ *  linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
  *
  *  Copyright (C) 1999,2000 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
@@ -333,19 +334,19 @@ ENTRY(cpu_arm920_switch_mm)
 ENTRY(cpu_arm920_set_pte)
 	str	r1, [r0], #-2048		@ linux version
 
-	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
-	orr	r2, r2, #HPTE_TYPE_SMALL
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
+	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #LPTE_USER			@ User or Exec?
-	orrne	r2, r2, #HPTE_AP_READ
+	tst	r1, #L_PTE_USER			@ User?
+	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-	orreq	r2, r2, #HPTE_AP_WRITE
+	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
 	movne	r2, #0
 
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -359,25 +360,9 @@ ENTRY(cpu_arm920_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm920_name)
-	.ascii	"Arm920T"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm920_setup, #function
 __arm920_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -408,8 +393,9 @@ __arm920_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm920_setup, . - __arm920_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -427,6 +413,8 @@ arm920_processor_functions:
 	.word	cpu_arm920_set_pte
 	.size	arm920_processor_functions, . - arm920_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4t"
@@ -436,6 +424,24 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm920_name, #object
+cpu_arm920_name:
+	.ascii	"ARM920T"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm920_name, . - cpu_arm920_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm922.S

 /*
- *  linux/arch/arm/mm/arm922.S: MMU functions for ARM922
+ *  linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
  *
  *  Copyright (C) 1999,2000 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
@@ -29,6 +29,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
@@ -337,19 +338,19 @@ ENTRY(cpu_arm922_switch_mm)
 ENTRY(cpu_arm922_set_pte)
 	str	r1, [r0], #-2048		@ linux version
 
-	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
-	orr	r2, r2, #HPTE_TYPE_SMALL
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
+	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #LPTE_USER			@ User?
-	orrne	r2, r2, #HPTE_AP_READ
+	tst	r1, #L_PTE_USER			@ User?
+	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-	orreq	r2, r2, #HPTE_AP_WRITE
+	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
 	movne	r2, #0
 
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -363,25 +364,9 @@ ENTRY(cpu_arm922_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm922_name)
-	.ascii	"Arm922T"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm922_setup, #function
 __arm922_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -412,8 +397,9 @@ __arm922_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm922_setup, . - __arm922_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -431,6 +417,8 @@ arm922_processor_functions:
 	.word	cpu_arm922_set_pte
 	.size	arm922_processor_functions, . - arm922_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4t"
@@ -440,6 +428,24 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm922_name, #object
+cpu_arm922_name:
+	.ascii	"ARM922T"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm922_name, . - cpu_arm922_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-arm926.S

@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
 #include <asm/page.h>
@@ -337,19 +338,19 @@ ENTRY(cpu_arm926_switch_mm)
 ENTRY(cpu_arm926_set_pte)
 	str	r1, [r0], #-2048		@ linux version
 
-	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
+	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
-	orr	r2, r2, #HPTE_TYPE_SMALL
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
+	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #LPTE_USER			@ User?
-	orrne	r2, r2, #HPTE_AP_READ
+	tst	r1, #L_PTE_USER			@ User?
+	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
-	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
-	orreq	r2, r2, #HPTE_AP_WRITE
+	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
+	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
 
-	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
+	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
 	movne	r2, #0
 
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -365,28 +366,9 @@ ENTRY(cpu_arm926_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-ENTRY(cpu_arm926_name)
-	.ascii	"ARM926EJ-S"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
-	.ascii	"i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	.ascii	"d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-	.ascii	"(wt)"
-#else
-	.ascii	"(wb)"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
-	.ascii	"RR"
-#endif
-#endif
-	.ascii	"\0"
-	.align
-
 	__INIT
 
+	.type	__arm926_setup, #function
 __arm926_setup:
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
@@ -427,8 +409,9 @@ __arm926_setup:
 	orr	r0, r0, #0x1000			@ ...1 .... .... ....
 #endif
 	mov	pc, lr
+	.size	__arm926_setup, . - __arm926_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -436,7 +419,7 @@ __arm926_setup:
  */
 	.type	arm926_processor_functions, #object
 arm926_processor_functions:
-	.word	v5tej_early_abort
+	.word	v5tj_early_abort
 	.word	cpu_arm926_proc_init
 	.word	cpu_arm926_proc_fin
 	.word	cpu_arm926_reset
@@ -446,6 +429,8 @@ arm926_processor_functions:
 	.word	cpu_arm926_set_pte
 	.size	arm926_processor_functions, . - arm926_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5tej"
@@ -455,14 +440,35 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_arm926_name, #object
+cpu_arm926_name:
+	.ascii	"ARM926EJ-S"
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+	.ascii	"i"
+#endif
+#ifndef CONFIG_CPU_DCACHE_DISABLE
+	.ascii	"d"
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	.ascii	"(wt)"
+#else
+	.ascii	"(wb)"
+#endif
+#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
+	.ascii	"RR"
+#endif
+#endif
+	.ascii	"\0"
+	.size	cpu_arm926_name, . - cpu_arm926_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr
 
 	.type	__arm926_proc_info,#object
 __arm926_proc_info:
-	.long	0x41009260
-	.long	0xff00fff0
+	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
+	.long	0xff0ffff0
 	.long	0x00000c1e			@ mmuflags
 	b	__arm926_setup
 	.long	cpu_arch_name

arch/arm/mm/proc-sa110.S

@@ -163,11 +163,11 @@ ENTRY(cpu_sa110_set_pte)
 
 	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
 	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #L_PTE_USER			@ User or Exec?
+	tst	r1, #L_PTE_USER			@ User?
 	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
 	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
@@ -182,13 +182,9 @@ ENTRY(cpu_sa110_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-cpu_sa110_name:
-	.asciz	"StrongARM-110"
-	.align
-
 	__INIT
 
+	.type	__sa110_setup, #function
 __sa110_setup:
 	mrc	p15, 0, r0, c1, c0		@ get control register v4
 	bic	r0, r0, #0x2e00			@ ..VI ZFRS BLDP WCAM
@@ -203,8 +199,9 @@ __sa110_setup:
 	mov	r10, #0x1f			@ Domains 0, 1 = client
 	mcr	p15, 0, r10, c3, c0		@ load domain access register
 	mov	pc, lr
+	.size	__sa110_setup, . - __sa110_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -218,16 +215,13 @@ ENTRY(sa110_processor_functions)
 	.word	cpu_sa110_proc_fin
 	.word	cpu_sa110_reset
 	.word	cpu_sa110_do_idle
-
-	/* dcache */
 	.word	cpu_sa110_dcache_clean_area
-
-	/* pgtable */
 	.word	cpu_sa110_switch_mm
 	.word	cpu_sa110_set_pte
-
 	.size	sa110_processor_functions, . - sa110_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4"
@@ -237,6 +231,12 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_sa110_name, #object
+cpu_sa110_name:
+	.asciz	"StrongARM-110"
+	.size	cpu_sa110_name, . - cpu_sa110_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-sa1100.S

 /*
- *  linux/arch/arm/mm/proc-sa110.S
+ *  linux/arch/arm/mm/proc-sa1100.S
  *
  *  Copyright (C) 1997-2002 Russell King
  *
@@ -187,11 +187,11 @@ ENTRY(cpu_sa1100_set_pte)
 
 	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
-	bic	r2, r1, #0xff0
-	bic	r2, r2, #3
+	bic	r2, r1, #PTE_SMALL_AP_MASK
+	bic	r2, r2, #PTE_TYPE_MASK
 	orr	r2, r2, #PTE_TYPE_SMALL
 
-	tst	r1, #L_PTE_USER			@ User or Exec?
+	tst	r1, #L_PTE_USER			@ User?
 	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
 
 	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
@@ -206,15 +206,9 @@ ENTRY(cpu_sa1100_set_pte)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
 	mov	pc, lr
 
-
-cpu_sa1100_name:
-	.asciz	"StrongARM-1100"
-cpu_sa1110_name:
-	.asciz	"StrongARM-1110"
-	.align
-
 	__INIT
 
+	.type	__sa1100_setup, #function
 __sa1100_setup:
 	mov	r10, #0
 	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
@@ -229,8 +223,9 @@ __sa1100_setup:
 	orr	r0, r0, #0x003d
 	orr	r0, r0, #0x3100			@ ..11 ...1 ..11 11.1
 	mov	pc, lr
+	.size	__sa1100_setup, . - __sa1100_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -252,6 +247,8 @@ ENTRY(sa1100_processor_functions)
 	.word	cpu_sa1100_set_pte
 	.size	sa1100_processor_functions, . - sa1100_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv4"
@@ -261,6 +258,17 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v4"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_sa1100_name, #object
+cpu_sa1100_name:
+	.asciz	"StrongARM-1100"
+	.size	cpu_sa1100_name, . - cpu_sa1100_name
+
+	.type	cpu_sa1110_name, #object
+cpu_sa1110_name:
+	.asciz	"StrongARM-1110"
+	.size	cpu_sa1110_name, . - cpu_sa1110_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/proc-xscale.S

@@ -236,6 +236,9 @@ ENTRY(xscale_flush_user_cache_range)
  *
  *	- start  - virtual start address
  *	- end	 - virtual end address
+ *
+ *	Note: single I-cache line invalidation isn't used here since
+ *	it also trashes the mini I-cache used by JTAG debuggers.
  */
 ENTRY(xscale_coherent_kern_range)
 	bic	r0, r0, #CACHELINESIZE - 1
@@ -568,22 +571,11 @@ ENTRY(cpu_xscale_set_pte)
 
 	.ltorg
 
-cpu_80200_name:
-	.asciz	"XScale-80200"
-
-cpu_80321_name:
-	.asciz	"XScale-IOP80321"
-
-cpu_pxa250_name:
-	.asciz	"XScale-PXA250"
-
-cpu_pxa210_name:
-	.asciz	"XScale-PXA210"
-
 	.align
 
 	__INIT
 
+	.type	__xscale_setup, #function
 __xscale_setup:
 	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 	msr	cpsr_c, r0
@@ -602,8 +594,9 @@ __xscale_setup:
 	orr	r0, r0, #0x0005			@ .... .... .... .C.M
 	orr	r0, r0, #0x3900			@ ..VI Z..S .... ....
 	mov	pc, lr
+	.size	__xscale_setup, . - __xscale_setup
 
-	.text
+	__INITDATA
 
 /*
  * Purpose : Function pointers used to access above functions - all calls
@@ -612,7 +605,7 @@ __xscale_setup:
 
 	.type	xscale_processor_functions, #object
 ENTRY(xscale_processor_functions)
-	.word	xscale_abort
+	.word	v5t_early_abort
 	.word	cpu_xscale_proc_init
 	.word	cpu_xscale_proc_fin
 	.word	cpu_xscale_reset
@@ -622,6 +615,8 @@ ENTRY(xscale_processor_functions)
 	.word	cpu_xscale_set_pte
 	.size	xscale_processor_functions, . - xscale_processor_functions
 
+	.section ".rodata"
+
 	.type	cpu_arch_name, #object
 cpu_arch_name:
 	.asciz	"armv5te"
@@ -631,6 +626,27 @@ cpu_arch_name:
 cpu_elf_name:
 	.asciz	"v5"
 	.size	cpu_elf_name, . - cpu_elf_name
+
+	.type	cpu_80200_name, #object
+cpu_80200_name:
+	.asciz	"XScale-80200"
+	.size	cpu_80200_name, . - cpu_80200_name
+
+	.type	cpu_80321_name, #object
+cpu_80321_name:
+	.asciz	"XScale-IOP80321"
+	.size	cpu_80321_name, . - cpu_80321_name
+
+	.type	cpu_pxa250_name, #object
+cpu_pxa250_name:
+	.asciz	"XScale-PXA250"
+	.size	cpu_pxa250_name, . - cpu_pxa250_name
+
+	.type	cpu_pxa210_name, #object
+cpu_pxa210_name:
+	.asciz	"XScale-PXA210"
+	.size	cpu_pxa210_name, . - cpu_pxa210_name
+
 	.align
 
 	.section ".proc.info", #alloc, #execinstr

arch/arm/mm/tlb-v3.S

@@ -42,7 +42,7 @@ ENTRY(v3_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v3_tlb_fns, #object
 ENTRY(v3_tlb_fns)

arch/arm/mm/tlb-v4.S

@@ -34,7 +34,6 @@ ENTRY(v4_flush_user_tlb_range)
 	act_mm	r3				@ get current->active_mm
 	eors	r3, ip, r3				@ == mm ?
 	movne	pc, lr				@ no, we dont do anything
-	vma_vm_flags ip, r2
 .v4_flush_kern_tlb_range:
 	bic	r0, r0, #0x0ff
 	bic	r0, r0, #0xf00
@@ -56,7 +55,7 @@ ENTRY(v4_flush_user_tlb_range)
 .globl v4_flush_kern_tlb_range
 .equ v4_flush_kern_tlb_range, .v4_flush_kern_tlb_range
 
-	__INIT
+	__INITDATA
 
 	.type	v4_tlb_fns, #object
 ENTRY(v4_tlb_fns)

arch/arm/mm/tlb-v4wb.S

@@ -67,7 +67,7 @@ ENTRY(v4wb_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v4wb_tlb_fns, #object
 ENTRY(v4wb_tlb_fns)

arch/arm/mm/tlb-v4wbi.S

@@ -58,7 +58,7 @@ ENTRY(v4wbi_flush_kern_tlb_range)
 	blo	1b
 	mov	pc, lr
 
-	__INIT
+	__INITDATA
 
 	.type	v4wbi_tlb_fns, #object
 ENTRY(v4wbi_tlb_fns)

arch/arm/tools/mach-types

@@ -6,7 +6,7 @@
 # To add an entry into this database, please see Documentation/arm/README,
 # or contact rmk@arm.linux.org.uk
 #
-# Last update: Sun Aug 3 16:26:10 2003
+# Last update: Thu Sep 18 17:15:55 2003
 #
 # machine_is_xxx	CONFIG_xxxx		MACH_TYPE_xxx		number
 #
@@ -367,3 +367,21 @@ cx861xx			ARCH_CX861XX		CX861XX			355
 ixp2000			ARCH_IXP2000		IXP2000			356
 xda			SA1100_XDA		XDA			357
 csir_ims		ARCH_CSIR_IMS		CSIR_IMS		358
+ixp421_dnaeeth		ARCH_IXP421_DNAEETH	IXP421_DNAEETH		359
+pocketserv9200		ARCH_POCKETSERV9200	POCKETSERV9200		360
+toto			ARCH_TOTO		TOTO			361
+s3c2440			ARCH_S3C2440		S3C2440			362
+ks8695p			ARCH_KS8695P		KS8695P			363
+se4000			ARCH_SE4000		SE4000			364
+quadriceps		ARCH_QUADRICEPS		QUADRICEPS		365
+bronco			ARCH_BRONCO		BRONCO			366
+esl_wireless_tab	ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET	367
+esl_sofcomp		ARCH_ESL_SOFCOMP	ESL_SOFCOMP		368
+s5c7375			ARCH_S5C7375		S5C7375			369
+spearhead		ARCH_SPEARHEAD		SPEARHEAD		370
+pantera			ARCH_PANTERA		PANTERA			371
+prayoglite		ARCH_PRAYOGLITE		PRAYOGLITE		372
+gumstik			ARCH_GUMSTIK		GUMSTIK			373
+rcube			ARCH_RCUBE		RCUBE			374
+rea_olv			ARCH_REA_OLV		REA_OLV			375
+pxa_iphone		ARCH_PXA_IPHONE		PXA_IPHONE		376

arch/i386/kernel/cpu/cpufreq/acpi.c

@@ -24,6 +24,7 @@
  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
+#include <linux/config.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>