Commit 0a53f169 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/ppc64: Use preempt_schedule_irq instead of preempt_schedule
  powerpc: Minor cleanup to lib/Kconfig.debug
  powerpc: Minor cleanup to sound/ppc/Kconfig
  powerpc: Minor cleanup to init/Kconfig
  powerpc: Limit memory hotplug support to PPC64 Book-3S machines
  powerpc: Limit hugetlbfs support to PPC64 Book-3S machines
  powerpc: Fix compile errors found by new ppc64e_defconfig
  powerpc: Add a Book-3E 64-bit defconfig
  powerpc/booke: Fix xmon single step on PowerPC Book-E
  powerpc: Align vDSO base address
  powerpc: Fix segment mapping in vdso32
  powerpc/iseries: Remove compiler version dependent hack
  powerpc/perf_events: Fix priority of MSR HV vs PR bits
  powerpc/5200: Update defconfigs
  drivers/serial/mpc52xx_uart.c: Use UPIO_MEM rather than SERIAL_IO_MEM
  powerpc/boot/dts: drop obsolete 'fsl5200-clocking'
  of: Remove nested function
  mpc5200: support for the MAN mpc5200 based board mucmc52
  mpc5200: support for the MAN mpc5200 based board uc101
parents 7fecf0a1 40578fca
......@@ -210,7 +210,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
......
......@@ -199,7 +199,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
rtc@50 {
compatible = "at,24c08";
......
......@@ -247,7 +247,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
......@@ -256,7 +255,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200-sram";
......
......@@ -251,7 +251,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
......@@ -260,7 +259,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
......
......@@ -223,7 +223,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
......@@ -232,7 +231,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
};
sram@8000 {
......
......@@ -222,7 +222,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
rtc@68 {
compatible = "dallas,ds1339";
......
......@@ -209,7 +209,6 @@ i2c@1700 {
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
interrupt-parent = < &ipic >;
fsl5200-clocking;
};
i2c@1720 {
......@@ -220,7 +219,6 @@ i2c@1720 {
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
interrupt-parent = < &ipic >;
fsl5200-clocking;
};
i2c@1740 {
......@@ -231,7 +229,6 @@ i2c@1740 {
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
interrupt-parent = < &ipic >;
fsl5200-clocking;
};
i2ccontrol@1760 {
......
/*
* Manroland mucmc52 board Device Tree Source
*
* Copyright (C) 2009 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
* Copyright 2006-2007 Secret Lab Technologies Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "manroland,mucmc52";
compatible = "manroland,mucmc52";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
gpt0: timer@600 { // GPT 0 in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2000 { /* PSC1 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
};
serial@2200 { /* PSC2 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2200 0x100>;
interrupts = <2 2 0>;
};
serial@2c00 { /* PSC6 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
compatible = "intel,lxt971";
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
hwmon@2c {
compatible = "ad,adm9240";
reg = <0x2c>;
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
pci@f0000d00 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
0x8000 0 0 1 &mpc5200_pic 0 3 3
0x8000 0 0 2 &mpc5200_pic 0 3 3
0x8000 0 0 3 &mpc5200_pic 0 2 3
0x8000 0 0 4 &mpc5200_pic 0 1 3
>;
clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>;
bus-range = <0 0>;
ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
};
localbus {
compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff800000 0x00800000
1 0 0x80000000 0x00800000
3 0 0x80000000 0x00800000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x00800000>;
bank-width = <4>;
device-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "DTS";
reg = <0x0 0x00100000>;
};
partition@100000 {
label = "Kernel";
reg = <0x100000 0x00200000>;
};
partition@300000 {
label = "RootFS";
reg = <0x00300000 0x00200000>;
};
partition@500000 {
label = "user";
reg = <0x00500000 0x00200000>;
};
partition@700000 {
label = "U-Boot";
reg = <0x00700000 0x00040000>;
};
partition@740000 {
label = "Env";
reg = <0x00740000 0x00020000>;
};
partition@760000 {
label = "red. Env";
reg = <0x00760000 0x00020000>;
};
partition@780000 {
label = "reserve";
reg = <0x00780000 0x00080000>;
};
};
simple100: gpio-controller-100@3,600100 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600100 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple104: gpio-controller-104@3,600104 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600104 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple200: gpio-controller-200@3,600200 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600200 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple201: gpio-controller-201@3,600201 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600201 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple202: gpio-controller-202@3,600202 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600202 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple203: gpio-controller-203@3,600203 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600203 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple204: gpio-controller-204@3,600204 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600204 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple206: gpio-controller-206@3,600206 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600206 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple207: gpio-controller-207@3,600207 {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x00600207 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
simple20f: gpio-controller-20f@3,60020f {
compatible = "manroland,mucmc52-aux-gpio";
reg = <3 0x0060020f 0x1>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
......@@ -244,7 +244,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
......@@ -253,7 +252,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
......
......@@ -244,7 +244,6 @@ i2c@3d00 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
fsl5200-clocking;
};
i2c@3d40 {
......@@ -253,7 +252,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
......
......@@ -160,7 +160,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl5200-clocking;
rtc@68 {
compatible = "dallas,ds1307";
......
/*
* Manroland uc101 board Device Tree Source
*
* Copyright (C) 2009 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
* Copyright 2006-2007 Secret Lab Technologies Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "manroland,uc101";
compatible = "manroland,uc101";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
gpt0: timer@600 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2000 { /* PSC1 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
};
serial@2200 { /* PSC2 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2200 0x100>;
interrupts = <2 2 0>;
};
serial@2c00 { /* PSC6 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
};
ethernet@3000 {
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
phy-handle = <&phy0>;
};
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
phy0: ethernet-phy@0 {
compatible = "intel,lxt971";
reg = <0>;
};
};
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
};
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
fsl,preserve-clocking;
clock-frequency = <400000>;
hwmon@2c {
compatible = "ad,adm9240";
reg = <0x2c>;
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
localbus {
compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff800000 0x00800000
1 0 0x80000000 0x00800000
3 0 0x80000000 0x00800000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x00800000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "DTS";
reg = <0x0 0x00100000>;
};
partition@100000 {
label = "Kernel";
reg = <0x100000 0x00200000>;
};
partition@300000 {
label = "RootFS";
reg = <0x00300000 0x00200000>;
};
partition@500000 {
label = "user";
reg = <0x00500000 0x00200000>;
};
partition@700000 {
label = "U-Boot";
reg = <0x00700000 0x00040000>;
};
partition@740000 {
label = "Env";
reg = <0x00740000 0x00010000>;
};
partition@750000 {
label = "red. Env";
reg = <0x00750000 0x00010000>;
};
partition@760000 {
label = "reserve";
reg = <0x00760000 0x000a0000>;
};
};
};
};
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......@@ -658,42 +658,43 @@ do_work:
cmpdi r0,0
crandc eq,cr1*4+eq,eq
bne restore
/* here we are preempting the current task */
1:
#ifdef CONFIG_TRACE_IRQFLAGS
bl .trace_hardirqs_on
/* Note: we just clobbered r10 which used to contain the previous
* MSR before the hard-disabling done by the caller of do_work.
* We don't have that value anymore, but it doesn't matter as
* we will hard-enable unconditionally, we can just reload the
* current MSR into r10
/* Here we are preempting the current task.
*
* Ensure interrupts are soft-disabled. We also properly mark
* the PACA to reflect the fact that they are hard-disabled
* and trace the change
*/
mfmsr r10
#endif /* CONFIG_TRACE_IRQFLAGS */
li r0,1
li r0,0
stb r0,PACASOFTIRQEN(r13)
stb r0,PACAHARDIRQEN(r13)
TRACE_DISABLE_INTS
/* Call the scheduler with soft IRQs off */
1: bl .preempt_schedule_irq
/* Hard-disable interrupts again (and update PACA) */
#ifdef CONFIG_PPC_BOOK3E
wrteei 1
bl .preempt_schedule
wrteei 0
#else
ori r10,r10,MSR_EE
mtmsrd r10,1 /* reenable interrupts */
bl .preempt_schedule
mfmsr r10
clrrdi r9,r1,THREAD_SHIFT
rldicl r10,r10,48,1 /* disable interrupts again */
rldicl r10,r10,48,1
rotldi r10,r10,16
mtmsrd r10,1
#endif /* CONFIG_PPC_BOOK3E */
li r0,0
stb r0,PACAHARDIRQEN(r13)
/* Re-test flags and eventually loop */
clrrdi r9,r1,THREAD_SHIFT
ld r4,TI_FLAGS(r9)
andi. r0,r4,_TIF_NEED_RESCHED
bne 1b
b restore
user_work:
#endif
#endif /* CONFIG_PREEMPT */
/* Enable interrupts */
#ifdef CONFIG_PPC_BOOK3E
wrteei 1
......
......@@ -97,7 +97,9 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
* to do an appropriate TLB flush here too
*/
if (bus->self) {
#ifdef CONFIG_PPC_STD_MMU_64
struct resource *res = bus->resource[0];
#endif
pr_debug("IO unmapping for PCI-PCI bridge %s\n",
pci_name(bus->self));
......
......@@ -116,20 +116,23 @@ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
static inline u32 perf_get_misc_flags(struct pt_regs *regs)
{
unsigned long mmcra = regs->dsisr;
unsigned long sihv = MMCRA_SIHV;
unsigned long sipr = MMCRA_SIPR;
if (TRAP(regs) != 0xf00)
return 0; /* not a PMU interrupt */
if (ppmu->flags & PPMU_ALT_SIPR) {
if (mmcra & POWER6_MMCRA_SIHV)
return PERF_RECORD_MISC_HYPERVISOR;
return (mmcra & POWER6_MMCRA_SIPR) ?
PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL;
sihv = POWER6_MMCRA_SIHV;
sipr = POWER6_MMCRA_SIPR;
}
if (mmcra & MMCRA_SIHV)
/* PR has priority over HV, so order below is important */
if (mmcra & sipr)
return PERF_RECORD_MISC_USER;
if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
return PERF_RECORD_MISC_HYPERVISOR;
return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER :
PERF_RECORD_MISC_KERNEL;
return PERF_RECORD_MISC_KERNEL;
}
/*
......
......@@ -1172,7 +1172,7 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
unsigned long base = mm->brk;
unsigned long ret;
#ifdef CONFIG_PPC64
#ifdef CONFIG_PPC_STD_MMU_64
/*
* If we are using 1TB segments and we are allowed to randomise
* the heap, we can put it above 1TB so it is backed by a 1TB
......
......@@ -57,7 +57,6 @@
#include <asm/cache.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/mmu-hash64.h>
#include <asm/firmware.h>
#include <asm/xmon.h>
#include <asm/udbg.h>
......
......@@ -50,6 +50,9 @@
/* Max supported size for symbol names */
#define MAX_SYMNAME 64
/* The alignment of the vDSO */
#define VDSO_ALIGNMENT (1 << 16)
extern char vdso32_start, vdso32_end;
static void *vdso32_kbase = &vdso32_start;
static unsigned int vdso32_pages;
......@@ -231,15 +234,21 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
* pick a base address for the vDSO in process space. We try to put it
* at vdso_base which is the "natural" base for it, but we might fail
* and end up putting it elsewhere.
* Add enough to the size so that the result can be aligned.
*/
down_write(&mm->mmap_sem);
vdso_base = get_unmapped_area(NULL, vdso_base,
vdso_pages << PAGE_SHIFT, 0, 0);
(vdso_pages << PAGE_SHIFT) +
((VDSO_ALIGNMENT - 1) & PAGE_MASK),
0, 0);
if (IS_ERR_VALUE(vdso_base)) {
rc = vdso_base;
goto fail_mmapsem;
}
/* Add required alignment. */
vdso_base = ALIGN(vdso_base, VDSO_ALIGNMENT);
/*
* Put vDSO base into mm struct. We need to do this before calling
* install_special_mapping or the perf counter mmap tracking code
......
......@@ -25,7 +25,7 @@ SECTIONS
. = ALIGN(16);
.text : {
*(.text .stub .text.* .gnu.linkonce.t.* __ftr_alt_*)
}
} :text
PROVIDE(__etext = .);
PROVIDE(_etext = .);
PROVIDE(etext = .);
......@@ -56,7 +56,7 @@ SECTIONS
.fixup : { *(.fixup) }
.dynamic : { *(.dynamic) } :text :dynamic
.got : { *(.got) }
.got : { *(.got) } :text
.plt : { *(.plt) }
_end = .;
......
......@@ -51,6 +51,8 @@ static void __init mpc5200_simple_setup_arch(void)
/* list of the supported boards */
static char *board[] __initdata = {
"intercontrol,digsy-mtc",
"manroland,mucmc52",
"manroland,uc101",
"phytec,pcm030",
"phytec,pcm032",
"promess,motionpro",
......
EXTRA_CFLAGS += -mno-minimal-toc
extra-y += dt.o
obj-y += exception.o
obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt_mod.o mf.o lpevents.o \
obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt.o mf.o lpevents.o \
hvcall.o proc.o htab.o iommu.o misc.o irq.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_VIOPATH) += viopath.o vio.o
obj-$(CONFIG_MODULES) += ksyms.o
quiet_cmd_dt_strings = DT_STR $@
cmd_dt_strings = $(OBJCOPY) --rename-section .rodata.str1.8=.dt_strings \
$< $@
$(obj)/dt_mod.o: $(obj)/dt.o
$(call if_changed,dt_strings)
......@@ -51,11 +51,16 @@
/*
* These are created by the linker script at the start and end
* of the section containing all the strings from this file.
* of the section containing all the strings marked with the DS macro.
*/
extern char __dt_strings_start[];
extern char __dt_strings_end[];
#define DS(s) ({ \
static const char __s[] __attribute__((section(".dt_strings"))) = s; \
__s; \
})
struct iseries_flat_dt {
struct boot_param_header header;
u64 reserve_map[2];
......@@ -64,9 +69,8 @@ struct iseries_flat_dt {
static void * __initdata dt_data;
/*
* Putting these strings here keeps them out of the section
* that we rename to .dt_strings using objcopy and capture
* for the strings blob of the flattened device tree.
* Putting these strings here keeps them out of the .dt_strings section
* that we capture for the strings blob of the flattened device tree.
*/
static char __initdata device_type_cpu[] = "cpu";
static char __initdata device_type_memory[] = "memory";
......@@ -173,7 +177,7 @@ static void __init dt_start_node(struct iseries_flat_dt *dt, const char *name)
#define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
static void __init dt_prop(struct iseries_flat_dt *dt, const char *name,
static void __init __dt_prop(struct iseries_flat_dt *dt, const char *name,
const void *data, int len)
{
unsigned long offset;
......@@ -191,44 +195,32 @@ static void __init dt_prop(struct iseries_flat_dt *dt, const char *name,
/* The actual data. */
dt_push_bytes(dt, data, len);
}
#define dt_prop(dt, name, data, len) __dt_prop((dt), DS(name), (data), (len))
static void __init dt_prop_str(struct iseries_flat_dt *dt, const char *name,
const char *data)
{
dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */
}
#define dt_prop_str(dt, name, data) \
dt_prop((dt), name, (data), strlen((data)) + 1); /* + 1 for NULL */
static void __init dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
static void __init __dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
u32 data)
{
dt_prop(dt, name, &data, sizeof(u32));
__dt_prop(dt, name, &data, sizeof(u32));
}
#define dt_prop_u32(dt, name, data) __dt_prop_u32((dt), DS(name), (data))
static void __init __maybe_unused dt_prop_u64(struct iseries_flat_dt *dt,
const char *name,
u64 data)
static void __init __maybe_unused __dt_prop_u64(struct iseries_flat_dt *dt,
const char *name, u64 data)
{
dt_prop(dt, name, &data, sizeof(u64));
__dt_prop(dt, name, &data, sizeof(u64));
}
#define dt_prop_u64(dt, name, data) __dt_prop_u64((dt), DS(name), (data))
static void __init dt_prop_u64_list(struct iseries_flat_dt *dt,
const char *name, u64 *data, int n)
{
dt_prop(dt, name, data, sizeof(u64) * n);
}
#define dt_prop_u64_list(dt, name, data, n) \
dt_prop((dt), name, (data), sizeof(u64) * (n))
static void __init dt_prop_u32_list(struct iseries_flat_dt *dt,
const char *name, u32 *data, int n)
{
dt_prop(dt, name, data, sizeof(u32) * n);
}
#define dt_prop_u32_list(dt, name, data, n) \
dt_prop((dt), name, (data), sizeof(u32) * (n))
#ifdef notyet
static void __init dt_prop_empty(struct iseries_flat_dt *dt, const char *name)
{
dt_prop(dt, name, NULL, 0);
}
#endif
#define dt_prop_empty(dt, name) dt_prop((dt), name, NULL, 0)
static void __init dt_cpus(struct iseries_flat_dt *dt)
{
......
......@@ -517,6 +517,15 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
in_xmon = 0;
#endif
#ifdef CONFIG_BOOKE
if (regs->msr & MSR_DE) {
bp = at_breakpoint(regs->nip);
if (bp != NULL) {
regs->nip = (unsigned long) &bp->instr[0];
atomic_inc(&bp->ref_count);
}
}
#else
if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
bp = at_breakpoint(regs->nip);
if (bp != NULL) {
......@@ -530,7 +539,7 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
}
}
}
#endif
insert_cpu_bpts();
local_irq_restore(flags);
......@@ -894,6 +903,14 @@ cmds(struct pt_regs *excp)
}
}
#ifdef CONFIG_BOOKE
static int do_step(struct pt_regs *regs)
{
regs->msr |= MSR_DE;
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
return 1;
}
#else
/*
* Step a single instruction.
* Some instructions we emulate, others we execute with MSR_SE set.
......@@ -924,6 +941,7 @@ static int do_step(struct pt_regs *regs)
regs->msr |= MSR_SE;
return 1;
}
#endif
static void bootcmds(void)
{
......
......@@ -97,6 +97,12 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
}
EXPORT_SYMBOL(of_mdiobus_register);
/* Helper function for of_phy_find_device */
static int of_phy_match(struct device *dev, void *phy_np)
{
return dev_archdata_get_node(&dev->archdata) == phy_np;
}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
......@@ -106,15 +112,10 @@ EXPORT_SYMBOL(of_mdiobus_register);
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
int match(struct device *dev, void *phy_np)
{
return dev_archdata_get_node(&dev->archdata) == phy_np;
}
if (!phy_np)
return NULL;
d = bus_find_device(&mdio_bus_type, NULL, phy_np, match);
d = bus_find_device(&mdio_bus_type, NULL, phy_np, of_phy_match);
return d ? to_phy_device(d) : NULL;
}
EXPORT_SYMBOL(of_phy_find_device);
......
......@@ -705,7 +705,7 @@ mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
return -EINVAL;
if ((ser->irq != port->irq) ||
(ser->io_type != SERIAL_IO_MEM) ||
(ser->io_type != UPIO_MEM) ||
(ser->baud_base != port->uartclk) ||
(ser->iomem_base != (void *)port->mapbase) ||
(ser->hub6 != 0))
......
......@@ -135,7 +135,7 @@ config TMPFS_POSIX_ACL
config HUGETLBFS
bool "HugeTLB file system support"
depends on X86 || IA64 || PPC64 || SPARC64 || (SUPERH && MMU) || \
depends on X86 || IA64 || PPC_BOOK3S_64 || SPARC64 || (SUPERH && MMU) || \
(S390 && 64BIT) || SYS_SUPPORTS_HUGETLBFS || BROKEN
help
hugetlbfs is a filesystem backing for HugeTLB pages, based on
......
......@@ -297,7 +297,7 @@ config AUDIT
config AUDITSYSCALL
bool "Enable system-call auditing support"
depends on AUDIT && (X86 || PPC || PPC64 || S390 || IA64 || UML || SPARC64|| SUPERH)
depends on AUDIT && (X86 || PPC || S390 || IA64 || UML || SPARC64 || SUPERH)
default y if SECURITY_SELINUX
help
Enable low-overhead system-call auditing infrastructure that
......
......@@ -392,7 +392,7 @@ config DEBUG_KMEMLEAK_TEST
config DEBUG_PREEMPT
bool "Debug preemptible kernel"
depends on DEBUG_KERNEL && PREEMPT && (TRACE_IRQFLAGS_SUPPORT || PPC64)
depends on DEBUG_KERNEL && PREEMPT && TRACE_IRQFLAGS_SUPPORT
default y
help
If you say Y here then the kernel will use a debug variant of the
......
......@@ -129,7 +129,7 @@ config MEMORY_HOTPLUG
bool "Allow for memory hot-add"
depends on SPARSEMEM || X86_64_ACPI_NUMA
depends on HOTPLUG && !(HIBERNATION && !S390) && ARCH_ENABLE_MEMORY_HOTPLUG
depends on (IA64 || X86 || PPC64 || SUPERH || S390)
depends on (IA64 || X86 || PPC_BOOK3S_64 || SUPERH || S390)
comment "Memory hotplug is currently incompatible with Software Suspend"
depends on SPARSEMEM && HOTPLUG && HIBERNATION && !S390
......
......@@ -2,7 +2,7 @@
menuconfig SND_PPC
bool "PowerPC sound devices"
depends on PPC64 || PPC32
depends on PPC
default y
help
Support for sound devices specific to PowerPC architectures.
......
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