drm/amd/display: change the max clock level to 16

As the gfxclk for SMU11 can have at most 16 discrete levels.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dm_services_types.h

@@ -92,7 +92,7 @@ enum dm_pp_clock_type {
 	(clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
 	"Invalid"
 
-#define DM_PP_MAX_CLOCK_LEVELS 8
+#define DM_PP_MAX_CLOCK_LEVELS 16
 
 struct dm_pp_clock_levels {
 	uint32_t num_levels;