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Commit 11632a0e authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
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staging: rtl8192e: Cleanup checkpatch -f warnings and errors - Part III 

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 52629477
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Showing with 668 additions and 641 deletions
drivers/staging/rtl8192e/r8192E_dev.h
View file @ 11632a0e
......@@ -28,11 +28,12 @@
#include "r8190P_def.h"
u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc);
bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device* dev);
bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev);
bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev);
bool rtl8192_HalTxCheckStuck(struct net_device *dev);
bool rtl8192_HalRxCheckStuck(struct net_device *dev);
void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta, u32 *p_intb);
void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
u32 *p_intb);
void rtl8192_enable_rx(struct net_device *dev);
void rtl8192_enable_tx(struct net_device *dev);
void rtl8192_EnableInterrupt(struct net_device *dev);
......@@ -40,17 +41,22 @@ void rtl8192_DisableInterrupt(struct net_device *dev);
void rtl8192_ClearInterrupt(struct net_device *dev);
void rtl8192_InitializeVariables(struct net_device *dev);
void rtl8192e_start_beacon(struct net_device *dev);
void rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val);
void rtl8192_get_eeprom_size(struct net_device* dev);
void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val);
void rtl8192_get_eeprom_size(struct net_device *dev);
bool rtl8192_adapter_start(struct net_device *dev);
void rtl8192_link_change(struct net_device *dev);
void rtl8192_AllowAllDestAddr(struct net_device* dev, bool bAllowAllDA, bool WriteIntoReg);
void rtl8192_tx_fill_desc(struct net_device* dev, struct tx_desc * pdesc, struct cb_desc *cb_desc,
struct sk_buff* skb);
void rtl8192_tx_fill_cmd_desc(struct net_device* dev, struct tx_desc_cmd * entry,
struct cb_desc *cb_desc, struct sk_buff* skb);
bool rtl8192_rx_query_status_desc(struct net_device* dev, struct rtllib_rx_stats *stats,
struct rx_desc *pdesc, struct sk_buff* skb);
void rtl8192_AllowAllDestAddr(struct net_device *dev, bool bAllowAllDA,
bool WriteIntoReg);
void rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
struct cb_desc *cb_desc,
struct sk_buff *skb);
void rtl8192_tx_fill_cmd_desc(struct net_device *dev,
struct tx_desc_cmd *entry,
struct cb_desc *cb_desc, struct sk_buff *skb);
bool rtl8192_rx_query_status_desc(struct net_device *dev,
struct rtllib_rx_stats *stats,
struct rx_desc *pdesc,
struct sk_buff *skb);
void rtl8192_halt_adapter(struct net_device *dev, bool reset);
void rtl8192_update_ratr_table(struct net_device* dev);
void rtl8192_update_ratr_table(struct net_device *dev);
#endif
drivers/staging/rtl8192e/r8192E_firmware.c
View file @ 11632a0e
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_firmware.h
View file @ 11632a0e
......@@ -21,7 +21,7 @@
#define RTL8190_CPU_START_OFFSET 0x80
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 )
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8)
enum firmware_init_step {
FW_INIT_STEP0_BOOT = 0,
......@@ -63,7 +63,7 @@ struct rt_firmware {
u16 cmdpacket_frag_thresold;
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
#define MAX_FW_INIT_STEP 3
u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
u16 firmware_buf_size[MAX_FW_INIT_STEP];
};
......
drivers/staging/rtl8192e/r8192E_hw.h
View file @ 11632a0e
......@@ -109,7 +109,7 @@ enum _RTL8192Pci_HW {
#define MULRW_SHIFT 3
#define MXDMA2_RX_SHIFT 4
#define MXDMA2_TX_SHIFT 0
PMR = 0x00c,
PMR = 0x00c,
EPROM_CMD = 0x00e,
#define EPROM_CMD_RESERVED_MASK BIT5
#define EPROM_CMD_9356SEL BIT4
......@@ -141,7 +141,8 @@ enum _RTL8192Pci_HW {
SIFS = 0x03E,
TCR = 0x040,
RCR = 0x044,
#define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
#define RCR_ONLYERLPKT BIT31
#define RCR_ENCS2 BIT30
#define RCR_ENCS1 BIT29
......@@ -337,9 +338,9 @@ enum _RTL8192Pci_HW {
NHM_RPI_COUNTER5 = 0x269,
NHM_RPI_COUNTER6 = 0x26A,
NHM_RPI_COUNTER7 = 0x26B,
WFCRC0 = 0x2f0,
WFCRC1 = 0x2f4,
WFCRC2 = 0x2f8,
WFCRC0 = 0x2f0,
WFCRC1 = 0x2f4,
WFCRC2 = 0x2f8,
BW_OPMODE = 0x300,
#define BW_OPMODE_11J BIT0
......@@ -365,32 +366,32 @@ enum _RTL8192Pci_HW {
#define RETRY_LIMIT_LONG_SHIFT 0
TSFR = 0x308,
RRSR = 0x310,
#define RRSR_RSC_OFFSET 21
#define RRSR_RSC_OFFSET 21
#define RRSR_SHORT_OFFSET 23
#define RRSR_RSC_DUPLICATE 0x600000
#define RRSR_RSC_UPSUBCHNL 0x400000
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
#define RRSR_MCS2 BIT14
#define RRSR_MCS3 BIT15
#define RRSR_MCS4 BIT16
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
#define RRSR_MCS2 BIT14
#define RRSR_MCS3 BIT15
#define RRSR_MCS4 BIT16
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define BRSR_AckShortPmb BIT23
UFWP = 0x318,
RATR0 = 0x320,
......@@ -422,12 +423,15 @@ enum _RTL8192Pci_HW {
#define RATR_MCS13 0x02000000
#define RATR_MCS14 0x04000000
#define RATR_MCS15 0x08000000
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M
#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
RATR_24M | RATR_36M | RATR_48M | RATR_54M)
#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
RATR_MCS6 | RATR_MCS7)
#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
RATR_MCS14|RATR_MCS15)
DRIVER_RSSI = 0x32c,
......@@ -442,8 +446,8 @@ enum _RTL8192Pci_HW {
#define GPO 0x109
#define GPE 0x10a
#define HWSET_MAX_SIZE_92S 128
#define HWSET_MAX_SIZE_92S 128
#define ANAPAR_FOR_8192PciE 0x17
#define ANAPAR_FOR_8192PciE 0x17
#endif
drivers/staging/rtl8192e/r8192E_hwimg.c
View file @ 11632a0e
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