[ARM] Kirkwood: support L2 writeback mode

This patch allows booting Kirkwood with the L2 in writeback mode,
by reading the WT override bit from the L2 config register and
passing that into the Feroceon L2 init routine, instead of assuming
that the WT override bit will always be set
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

arch/arm/mach-kirkwood/common.c

@@ -313,6 +313,11 @@ static char * __init kirkwood_id(void)
 	return "unknown 88F6000 variant";
 }
 
+static int __init is_l2_writethrough(void)
+{
+	return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
+}
+
 void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
@@ -321,6 +326,6 @@ void __init kirkwood_init(void)
 	kirkwood_setup_cpu_mbus();
 
 #ifdef CONFIG_CACHE_FEROCEON_L2
-	feroceon_l2_init(1);
+	feroceon_l2_init(is_l2_writethrough());
 #endif
 }

include/asm-arm/arch-kirkwood/kirkwood.h

@@ -49,7 +49,6 @@
 #define BRIDGE_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x20000)
 #define  CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)
 #define   CPU_RESET		0x00000002
-//#define   L2_WRITETHROUGH	0x00020000
 #define  RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)
 #define   SOFT_RESET_OUT_EN	0x00000004
 #define  SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)
@@ -65,6 +64,8 @@
 #define   IRQ_CAUSE_HIGH_OFF	0x0010
 #define   IRQ_MASK_HIGH_OFF	0x0014
 #define  TIMER_VIRT_BASE	(BRIDGE_VIRT_BASE | 0x0300)
+#define  L2_CONFIG_REG		(BRIDGE_VIRT_BASE | 0x0128)
+#define   L2_WRITETHROUGH	0x00000010
 
 /*
  * Register Map