Commit 19aa2113 authored by Mike Rapoport's avatar Mike Rapoport Committed by Greg Kroah-Hartman

staging: sm750fb: set{Memory, Master}Clock: rename ulReg to reg

Remove HungarianCamelCase notation
Signed-off-by: default avatarMike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 90946e52
...@@ -79,7 +79,7 @@ static void setChipClock(unsigned int frequency) ...@@ -79,7 +79,7 @@ static void setChipClock(unsigned int frequency)
static void setMemoryClock(unsigned int frequency) static void setMemoryClock(unsigned int frequency)
{ {
unsigned int ulReg, divisor; unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
...@@ -95,24 +95,24 @@ static void setMemoryClock(unsigned int frequency) ...@@ -95,24 +95,24 @@ static void setMemoryClock(unsigned int frequency)
divisor = roundedDiv(get_mxclk_freq(), frequency); divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */ /* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE); reg = PEEK32(CURRENT_GATE);
switch (divisor) { switch (divisor) {
default: default:
case 1: case 1:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1); reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_1);
break; break;
case 2: case 2:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2); reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_2);
break; break;
case 3: case 3:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3); reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_3);
break; break;
case 4: case 4:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4); reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_4);
break; break;
} }
setCurrentGate(ulReg); setCurrentGate(reg);
} }
} }
...@@ -126,7 +126,7 @@ static void setMemoryClock(unsigned int frequency) ...@@ -126,7 +126,7 @@ static void setMemoryClock(unsigned int frequency)
*/ */
static void setMasterClock(unsigned int frequency) static void setMasterClock(unsigned int frequency)
{ {
unsigned int ulReg, divisor; unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
...@@ -142,24 +142,24 @@ static void setMasterClock(unsigned int frequency) ...@@ -142,24 +142,24 @@ static void setMasterClock(unsigned int frequency)
divisor = roundedDiv(get_mxclk_freq(), frequency); divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */ /* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE); reg = PEEK32(CURRENT_GATE);
switch (divisor) { switch (divisor) {
default: default:
case 3: case 3:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3); reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_3);
break; break;
case 4: case 4:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4); reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_4);
break; break;
case 6: case 6:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6); reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_6);
break; break;
case 8: case 8:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8); reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_8);
break; break;
} }
setCurrentGate(ulReg); setCurrentGate(reg);
} }
} }
......
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