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Commit 1a623a25 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Paul Mackerras
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PPC32: Forward-port support for new powermacs from 2.4 tree.

parent f5a61e07
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arch/ppc/platforms/pmac_feature.c
View file @ 1a623a25
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include/asm-ppc/keylargo.h
View file @ 1a623a25
......@@ -10,12 +10,13 @@
#define KL_PANGEA_REV 0x100
/* offset from base for feature control registers */
#define KEYLARGO_MBCR 0x34 /* Media bay control/status */
#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
#define KEYLARGO_FCR0 0x38
#define KEYLARGO_FCR1 0x3c
#define KEYLARGO_FCR2 0x40
#define KEYLARGO_FCR3 0x44
#define KEYLARGO_FCR4 0x48
#define KEYLARGO_FCR5 0x4c /* Pangea only */
/* GPIO registers */
#define KEYLARGO_GPIO_LEVELS0 0x50
......@@ -85,76 +86,111 @@
#define KL_MBCR_MB1_DEV_RESET 0x02000000
#define KL_MBCR_MB1_ENABLE 0x01000000
#define KL0_SCC_B_INTF_ENABLE 0x00000001
#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
#define KL0_SCC_A_INTF_ENABLE 0x00000002
#define KL0_SCC_SLOWPCLK 0x00000004
#define KL0_SCC_RESET 0x00000008
#define KL0_SCCA_ENABLE 0x00000010
#define KL0_SCCB_ENABLE 0x00000020
#define KL0_SCC_CELL_ENABLE 0x00000040
#define KL0_IRDA_HIGH_BAND 0x00000100
#define KL0_IRDA_SOURCE2_SEL 0x00000200
#define KL0_IRDA_SOURCE1_SEL 0x00000400
#define KL0_IRDA_RESET 0x00000800
#define KL0_IRDA_DEFAULT1 0x00001000
#define KL0_IRDA_DEFAULT0 0x00002000
#define KL0_IRDA_FAST_CONNECT 0x00004000
#define KL0_IRDA_ENABLE 0x00008000
#define KL0_IRDA_CLK32_ENABLE 0x00010000
#define KL0_IRDA_CLK19_ENABLE 0x00020000
#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
#define KL0_USB0_PAD_SUSPEND0 0x00040000
#define KL0_USB0_PAD_SUSPEND1 0x00080000
#define KL0_USB0_CELL_ENABLE 0x00100000
#define KL0_USB1_PAD_SUSPEND0 0x00400000
#define KL0_USB1_PAD_SUSPEND1 0x00800000
#define KL0_USB1_CELL_ENABLE 0x01000000
#define KL0_USB_REF_SUSPEND 0x10000000
#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
KL0_SCC_SLOWPCLK | \
KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
#define KL1_AUDIO_SEL_22MCLK 0x00000002
#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008
#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* Burgundy only ? */
#define KL1_AUDIO_CELL_ENABLE 0x00000040
#define KL1_AUDIO_CHOOSE 0x00000080 /* Burgundy only ? */
#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
#define KL1_I2S0_CELL_ENABLE 0x00000400
#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
#define KL1_I2S0_ENABLE 0x00002000
#define KL1_I2S1_CELL_ENABLE 0x00020000
#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
#define KL1_I2S1_ENABLE 0x00100000
#define KL1_EIDE0_ENABLE 0x00800000
#define KL1_EIDE0_RESET_N 0x01000000
#define KL1_EIDE1_ENABLE 0x04000000
#define KL1_EIDE1_RESET_N 0x08000000
#define KL1_UIDE_ENABLE 0x20000000
#define KL1_UIDE_RESET_N 0x40000000
#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
#define KL2_IOBUS_ENABLE 0x00000002
#define KL2_SLEEP_STATE_BIT 0x00000100
#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
#define KL2_MPIC_ENABLE 0x00020000
#define KL2_ALT_DATA_OUT 0x02000000
#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
#define KL2_MEM_IS_BIG 0x04000000
#define KL2_CARDSEL_16 0x08000000
#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001
#define KL3_SHUTDOWN_PLLKW6 0x00000002
#define KL3_SHUTDOWN_PLLKW4 0x00000004
#define KL3_SHUTDOWN_PLLKW35 0x00000008
#define KL3_SHUTDOWN_PLLKW12 0x00000010
#define KL3_PLL_RESET 0x00000020
#define KL3_SHUTDOWN_PLL2X 0x00000080
#define KL3_CLK66_ENABLE 0x00000100
#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
#define KL3_CLK49_ENABLE 0x00000200
#define KL3_CLK45_ENABLE 0x00000400
#define KL3_CLK31_ENABLE 0x00000800
#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
#define KL3_TIMER_CLK18_ENABLE 0x00001000
#define KL3_I2S1_CLK18_ENABLE 0x00002000
#define KL3_I2S0_CLK18_ENABLE 0x00004000
#define KL3_VIA_CLK16_ENABLE 0x00008000
#define KL3_STOPPING33_ENABLED 0x00080000
#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
/* Intrepid USB bus 2, port 0,1 */
#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
/* Port 0,1 : bus 0, port 2,3 : bus 1 */
#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
......@@ -165,3 +201,10 @@
#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
/* Pangea and Intrepid only */
#define KL5_VIA_USE_CLK31 0x000000001 /* Pangea Only */
#define KL5_SCC_USE_CLK31 0x000000002 /* Pangea Only */
#define KL5_PWM_CLK32_EN 0x000000004
#define KL5_CLK3_68_EN 0x000000010
#define KL5_CLK32_EN 0x000000020
include/asm-ppc/macio_asic.h 0 → 100644
View file @ 1a623a25
#ifndef __MACIO_ASIC_H__
#define __MACIO_ASIC_H__
#include <linux/device.h>
extern struct bus_type macio_bus_type;
/* MacIO device driver is defined later */
struct macio_driver;
struct macio_chip;
#define MACIO_DEV_COUNT_RESOURCE 8
#define MACIO_DEV_COUNT_IRQS 8
/*
* the macio_bus structure is used to describe a "virtual" bus
* within a MacIO ASIC. It's typically provided by a macio_pci_asic
* PCI device, but could be provided differently as well (nubus
* machines using a fake OF tree).
*/
struct macio_bus
{
struct macio_chip *chip; /* macio_chip (private use) */
struct pci_dev *pdev; /* PCI device hosting this bus */
struct list_head devices; /* list of devices on this bus */
};
/*
* the macio_dev structure is used to describe a device
* within an Apple MacIO ASIC.
*/
struct macio_dev
{
struct macio_bus *bus; /* virtual bus this device is on */
struct device_node *node; /* OF node */
struct macio_driver *driver; /* which driver allocated this device */
void *driver_data; /* placeholder for driver specific stuffs */
struct resource resources[MACIO_DEV_COUNT_RESOURCE]; /* I/O */
int irqs[MACIO_DEV_COUNT_IRQS];
struct device dev; /* Generic device interface */
};
#define to_macio_device(d) container_of(d, struct macio_dev, dev)
/*
* Struct used for matching a device
*/
struct macio_match
{
char *name;
char *type;
char *compatible;
};
#define MACIO_ANY_MATCH ((char *)-1L)
/*
* A driver for a mac-io chip based device
*/
struct macio_driver
{
struct list_head node;
char *name;
struct macio_match *match_table;
int (*probe)(struct macio_dev* dev, const struct macio_match *match);
int (*remove)(struct macio_dev* dev);
int (*suspend)(struct macio_dev* dev, u32 state, u32 level);
int (*resume)(struct macio_dev* dev, u32 level);
int (*shutdown)(struct macio_dev* dev);
struct device_driver driver;
};
#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
extern int macio_register_driver(struct macio_driver *);
extern void macio_unregister_driver(struct macio_driver *);
#endif /* __MACIO_ASIC_H__ */
include/asm-ppc/pmac_feature.h
View file @ 1a623a25
......@@ -31,10 +31,16 @@
#ifndef __PPC_ASM_PMAC_FEATURE_H
#define __PPC_ASM_PMAC_FEATURE_H
#include <asm/macio_asic.h>
/*
* Known Mac motherboard models
*
* Please, report any error here to benh@kernel.crashing.org, thanks !
*
* Note that I don't fully maintain this list for Core99 & MacRISC2
* and I'm considering removing all NewWorld entries from it and
* entirely rely on the model string.
*/
/* PowerSurge are the first generation of PCI Pmacs. This include
......@@ -85,10 +91,16 @@
#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook */
#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3) */
#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
#define PMAC_TYPE_EMAC 0x50 /* eMac */
#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
/* MacRisc2 with UniNorth 2.0 */
#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
#define PMAC_TYPE_WINDTUNNEL 0x81
/* MacRISC2 machines based on the Pangea chipset
*/
#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
......@@ -96,12 +108,18 @@
#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
/* MacRISC2 machines based on the Intrepid chipset
*/
#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
/*
* Motherboard flags
*/
#define PMAC_MB_CAN_SLEEP 0x00000001
#define PMAC_MB_HAS_FW_POWER 0x00000002
#define PMAC_MB_OLD_CORE99 0x00000004
#define PMAC_MB_MOBILE 0x00000008
/*
* Feature calls supported on pmac
......@@ -251,5 +269,60 @@ extern void pmac_feature_init(void);
#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x))
/*
* The part below is for use by macio_asic.c only, do not rely
* on the data structures or constants below in a normal driver
*
*/
#define MAX_MACIO_CHIPS 2
enum {
macio_unknown = 0,
macio_grand_central,
macio_ohare,
macio_ohareII,
macio_heathrow,
macio_gatwick,
macio_paddington,
macio_keylargo,
macio_pangea,
macio_intrepid,
};
struct macio_chip
{
struct device_node *of_node;
int type;
const char *name;
int rev;
volatile u32 *base;
unsigned long flags;
/* For use by macio_asic PCI driver */
struct macio_bus lbus;
};
extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
#define MACIO_FLAG_SCCA_ON 0x00000001
#define MACIO_FLAG_SCCB_ON 0x00000002
#define MACIO_FLAG_SCC_LOCKED 0x00000004
#define MACIO_FLAG_AIRPORT_ON 0x00000010
#define MACIO_FLAG_FW_SUPPORTED 0x00000020
extern struct macio_chip* macio_find(struct device_node* child, int type);
#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
#define MACIO_FCR8(macio, r) (((volatile u8*)((macio)->base)) + (r))
#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
#endif /* __PPC_ASM_PMAC_FEATURE_H */
#endif /* __KERNEL__ */
include/asm-ppc/uninorth.h
View file @ 1a623a25
......@@ -28,6 +28,7 @@
#define UNI_N_CFG_GART_INVAL 0x00000001
#define UNI_N_CFG_GART_ENABLE 0x00000100
#define UNI_N_CFG_GART_2xRESET 0x00010000
#define UNI_N_CFG_GART_DISSBADET 0x00020000
/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
* revision 1.5 (x4 AGP) may need further changes.
......@@ -94,6 +95,7 @@
#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
/* Power Management control */
#define UNI_N_POWER_MGT 0x0030
......
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