Commit 1c17ae8a authored by Divy Le Ray's avatar Divy Le Ray Committed by David S. Miller

cxgb3 - Set the CQ_ERR bit in CQ contexts.

The cxgb3 driver is incorrectly configuring the HW CQ context for CQ's
that use overflow-avoidance.  Namely the RDMA control CQ.  This results
in a bad DMA from the device to bus address 0.  The solution is to set
the CQ_ERR bit in the context for these types of CQs.
Signed-off-by: default avatarDivy Le Ray <divy@chelsio.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent b4687ff7
...@@ -106,6 +106,10 @@ ...@@ -106,6 +106,10 @@
#define V_CQ_GEN(x) ((x) << S_CQ_GEN) #define V_CQ_GEN(x) ((x) << S_CQ_GEN)
#define F_CQ_GEN V_CQ_GEN(1U) #define F_CQ_GEN V_CQ_GEN(1U)
#define S_CQ_ERR 30
#define V_CQ_ERR(x) ((x) << S_CQ_ERR)
#define F_CQ_ERR V_CQ_ERR(1U)
#define S_CQ_OVERFLOW_MODE 31 #define S_CQ_OVERFLOW_MODE 31
#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE) #define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U) #define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U)
......
...@@ -2046,7 +2046,8 @@ int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, ...@@ -2046,7 +2046,8 @@ int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
base_addr >>= 32; base_addr >>= 32;
t3_write_reg(adapter, A_SG_CONTEXT_DATA2, t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) | V_CQ_BASE_HI((u32) base_addr) | V_CQ_RSPQ(rspq) |
V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode)); V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) |
V_CQ_ERR(ovfl_mode));
t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
V_CQ_CREDIT_THRES(credit_thres)); V_CQ_CREDIT_THRES(credit_thres));
return t3_sge_write_context(adapter, id, F_CQ); return t3_sge_write_context(adapter, id, F_CQ);
......
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