Merge branch 'lorenzo/pci/rcar'

  - clean up clocks, MSI, IRQ mappings in R-Car probe failure paths (Marek
    Vasut)

  - poll more frequently (5us vs 5ms) while waiting for R-Car data link
    active (Marek Vasut)

  - use generic OF parsing interface in R-Car (Vladimir Zapolskiy)

  - add R-Car V3H (R8A77980) "compatible" string (Sergei Shtylyov)

  - add R-Car gen3 PHY support (Sergei Shtylyov)

  - improve R-Car PHYRDY polling (Sergei Shtylyov)

  - clean up R-Car macros (Marek Vasut)

  - use runtime PM for R-Car controller clock (Dien Pham)

* lorenzo/pci/rcar:
  PCI: rcar: Remove IRQ mappings in rcar_pcie_enable_msi() failpath
  PCI: rcar: Teardown MSI setup if rcar_pcie_enable() fails
  PCI: rcar: Add missing irq_dispose_mapping() into failpath
  PCI: rcar: Pull bus clock enable/disable from rcar_pcie_get_resources()
  PCI: rcar: Poll more often in rcar_pcie_wait_for_dl()
  PCI: rcar: Reuse generic pci_parse_request_of_pci_ranges() function
  DT: pci: rcar-pci: document R8A77980 bindings
  PCI: rcar: Factor out rcar_pcie_hw_init() call
  PCI: rcar: Add R-Car gen3 PHY support
  PCI: rcar: Remove PHYRDY polling from rcar_pcie_hw_init_h1()
  PCI: rcar: Poll PHYRDY in rcar_pcie_hw_init()
  PCI: rcar: Clean up the macros
  PCI: rcar: Use runtime PM to control controller clock

# Conflicts:
#	drivers/pci/host/pcie-rcar.c

Documentation/devicetree/bindings/pci/rcar-pci.txt

@@ -8,6 +8,7 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
 	    "renesas,pcie-r8a7793" for the R8A7793 SoC;
 	    "renesas,pcie-r8a7795" for the R8A7795 SoC;
 	    "renesas,pcie-r8a7796" for the R8A7796 SoC;
+	    "renesas,pcie-r8a77980" for the R8A77980 SoC;
 	    "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
 				     RZ/G1 compatible device.
 	    "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
@@ -32,6 +33,11 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
 	and PCIe bus clocks.
 - clock-names: from common clock binding: should be "pcie" and "pcie_bus".
 
+Optional properties:
+- phys: from common PHY binding: PHY phandle and specifier (only make sense
+	for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
+- phy-names: from common PHY binding: should be "pcie".
+
 Example:
 
 SoC-specific DT Entry: