wl12xx: Clamp byte mode transfers for 128x chips
On wl128x based devices, when TX packets are aggregated, each packet size must be aligned to the SDIO block size, and sent using block mode transfers. The block size is set to 256 bytes, which is less than the maximum possible byte transfer. Thus, if two small packets (< 256 bytes) are aggregated, the aggregation buffer size would be 512, and will be sent using byte mode transfers. This can have undesired side effects. Fix this by setting the MMC_QUIRK_BLKSZ_FOR_BYTE_MODE mmc card quirk. For 127x chips this has no effect, as the block size is set to 512 bytes. Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Ido Yariv <ido@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
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