Commit 1f60d114 authored by Sharat Masetty's avatar Sharat Masetty Committed by Rob Clark

drm: msm: a6xx: send opp instead of a frequency

This patch changes the plumbing to send the devfreq recommended opp rather
than the frequency. Also consolidate and rearrange the code in a6xx to set
the GPU frequency and the icc vote in preparation for the upcoming
changes for GPU->DDR scaling votes.
Signed-off-by: default avatarSharat Masetty <smasetty@codeaurora.org>
Signed-off-by: default avatarAkhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 369c4ef4
...@@ -103,17 +103,45 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) ...@@ -103,17 +103,45 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
} }
static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
{ {
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
int ret; u32 perf_index;
unsigned long gpu_freq;
int ret = 0;
gpu_freq = dev_pm_opp_get_freq(opp);
if (gpu_freq == gmu->freq)
return;
for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
if (gpu_freq == gmu->gpu_freqs[perf_index])
break;
gmu->current_perf_index = perf_index;
gmu->freq = gmu->gpu_freqs[perf_index];
/*
* This can get called from devfreq while the hardware is idle. Don't
* bring up the power if it isn't already active
*/
if (pm_runtime_get_if_in_use(gmu->dev) == 0)
return;
if (!gmu->legacy) {
a6xx_hfi_set_freq(gmu, perf_index);
icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
pm_runtime_put(gmu->dev);
return;
}
gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
((3 & 0xf) << 28) | index); ((3 & 0xf) << 28) | perf_index);
/* /*
* Send an invalid index as a vote for the bus bandwidth and let the * Send an invalid index as a vote for the bus bandwidth and let the
...@@ -134,37 +162,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) ...@@ -134,37 +162,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
* for now leave it at max so that the performance is nominal. * for now leave it at max so that the performance is nominal.
*/ */
icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
}
void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
u32 perf_index = 0;
if (freq == gmu->freq)
return;
for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
if (freq == gmu->gpu_freqs[perf_index])
break;
gmu->current_perf_index = perf_index;
gmu->freq = gmu->gpu_freqs[perf_index];
/*
* This can get called from devfreq while the hardware is idle. Don't
* bring up the power if it isn't already active
*/
if (pm_runtime_get_if_in_use(gmu->dev) == 0)
return;
if (gmu->legacy)
__a6xx_gmu_set_freq(gmu, perf_index);
else
a6xx_hfi_set_freq(gmu, perf_index);
pm_runtime_put(gmu->dev); pm_runtime_put(gmu->dev);
} }
...@@ -839,6 +836,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) ...@@ -839,6 +836,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
a6xx_gmu_rpmh_off(gmu); a6xx_gmu_rpmh_off(gmu);
} }
static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
{
struct dev_pm_opp *gpu_opp;
unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
if (IS_ERR_OR_NULL(gpu_opp))
return;
a6xx_gmu_set_freq(gpu, gpu_opp);
dev_pm_opp_put(gpu_opp);
}
int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
{ {
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
...@@ -898,10 +908,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) ...@@ -898,10 +908,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
enable_irq(gmu->hfi_irq); enable_irq(gmu->hfi_irq);
/* Set the GPU to the current freq */ /* Set the GPU to the current freq */
if (gmu->legacy) a6xx_gmu_set_initial_freq(gpu, gmu);
__a6xx_gmu_set_freq(gmu, gmu->current_perf_index);
else
a6xx_hfi_set_freq(gmu, gmu->current_perf_index);
/* /*
* "enable" the GX power domain which won't actually do anything but it * "enable" the GX power domain which won't actually do anything but it
......
...@@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); ...@@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq); void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
......
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
#include <generated/utsrelease.h> #include <generated/utsrelease.h>
#include <linux/string_helpers.h> #include <linux/string_helpers.h>
#include <linux/pm_opp.h>
#include <linux/devfreq.h> #include <linux/devfreq.h>
#include <linux/devcoredump.h> #include <linux/devcoredump.h>
#include <linux/sched/task.h> #include <linux/sched/task.h>
...@@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, ...@@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
return PTR_ERR(opp); return PTR_ERR(opp);
if (gpu->funcs->gpu_set_freq) if (gpu->funcs->gpu_set_freq)
gpu->funcs->gpu_set_freq(gpu, (u64)*freq); gpu->funcs->gpu_set_freq(gpu, opp);
else else
clk_set_rate(gpu->core_clk, *freq); clk_set_rate(gpu->core_clk, *freq);
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/interconnect.h> #include <linux/interconnect.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
#include "msm_drv.h" #include "msm_drv.h"
...@@ -61,7 +62,7 @@ struct msm_gpu_funcs { ...@@ -61,7 +62,7 @@ struct msm_gpu_funcs {
struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
int (*gpu_state_put)(struct msm_gpu_state *state); int (*gpu_state_put)(struct msm_gpu_state *state);
unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
struct msm_gem_address_space *(*create_address_space) struct msm_gem_address_space *(*create_address_space)
(struct msm_gpu *gpu, struct platform_device *pdev); (struct msm_gpu *gpu, struct platform_device *pdev);
}; };
......
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