Commit 2422a9b3 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab

V4L/DVB (7370): Add basic support for Prolink Pixelview MPEG 8000GT

TV reception ok. S-video and Composite not tested. Audio not tested.
IR not implemented yet.
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@infradead.org>
parent aba360d8
...@@ -64,3 +64,4 @@ ...@@ -64,3 +64,4 @@
63 -> Geniatech X8000-MT DVBT [14f1:8852] 63 -> Geniatech X8000-MT DVBT [14f1:8852]
64 -> DViCO FusionHDTV DVB-T PRO [18ac:db30] 64 -> DViCO FusionHDTV DVB-T PRO [18ac:db30]
65 -> DViCO FusionHDTV 7 Gold [18ac:d610] 65 -> DViCO FusionHDTV 7 Gold [18ac:d610]
66 -> Prolink Pixelview MPEG 8000GT [1554:4935]
...@@ -1591,6 +1591,29 @@ static const struct cx88_board cx88_boards[] = { ...@@ -1591,6 +1591,29 @@ static const struct cx88_board cx88_boards[] = {
.gpio0 = 0x16d9, .gpio0 = 0x16d9,
}}, }},
}, },
[CX88_BOARD_PROLINK_PV_8000GT] = {
.name = "Prolink Pixelview MPEG 8000GT",
.tuner_type = TUNER_XC2028,
.tuner_addr = 0x61,
.input = { {
.type = CX88_VMUX_TELEVISION,
.vmux = 0,
.gpio0 = 0x0ff,
.gpio2 = 0x0cfb,
}, {
.type = CX88_VMUX_COMPOSITE1,
.vmux = 1,
.gpio2 = 0x0cfb,
}, {
.type = CX88_VMUX_SVIDEO,
.vmux = 2,
.gpio2 = 0x0cfb,
} },
.radio = {
.type = CX88_RADIO,
.gpio2 = 0x0cfb,
},
},
}; };
/* ------------------------------------------------------------------ */ /* ------------------------------------------------------------------ */
...@@ -1928,11 +1951,15 @@ static const struct cx88_subid cx88_subids[] = { ...@@ -1928,11 +1951,15 @@ static const struct cx88_subid cx88_subids[] = {
.subvendor = 0x14f1, .subvendor = 0x14f1,
.subdevice = 0x8852, .subdevice = 0x8852,
.card = CX88_BOARD_GENIATECH_X8000_MT, .card = CX88_BOARD_GENIATECH_X8000_MT,
},{ }, {
.subvendor = 0x18ac, .subvendor = 0x18ac,
.subdevice = 0xd610, .subdevice = 0xd610,
.card = CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD, .card = CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD,
} }, {
.subvendor = 0x1554,
.subdevice = 0x4935,
.card = CX88_BOARD_PROLINK_PV_8000GT,
},
}; };
/* ----------------------------------------------------------------------- */ /* ----------------------------------------------------------------------- */
...@@ -2063,9 +2090,10 @@ static void gdi_eeprom(struct cx88_core *core, u8 *eeprom_data) ...@@ -2063,9 +2090,10 @@ static void gdi_eeprom(struct cx88_core *core, u8 *eeprom_data)
/* ------------------------------------------------------------------- */ /* ------------------------------------------------------------------- */
/* some Divco specific stuff */ /* some Divco specific stuff */
static int cx88_dvico_xc2028_callback(void *ptr, int command, int arg) static int cx88_dvico_xc2028_callback(void *priv, int command, int arg)
{ {
struct cx88_core *core = ptr; struct i2c_algo_bit_data *i2c_algo = priv;
struct cx88_core *core = i2c_algo->data;
switch (command) { switch (command) {
case XC2028_TUNER_RESET: case XC2028_TUNER_RESET:
...@@ -2113,6 +2141,28 @@ static int cx88_xc3028_geniatech_tuner_callback(void *priv, int command, int mod ...@@ -2113,6 +2141,28 @@ static int cx88_xc3028_geniatech_tuner_callback(void *priv, int command, int mod
return -EINVAL; return -EINVAL;
} }
/* ------------------------------------------------------------------- */
/* some Divco specific stuff */
static int cx88_pv_8000gt_callback(void *priv, int command, int arg)
{
struct i2c_algo_bit_data *i2c_algo = priv;
struct cx88_core *core = i2c_algo->data;
switch (command) {
case XC2028_TUNER_RESET:
cx_write(MO_GP2_IO, 0xcf7);
mdelay(50);
cx_write(MO_GP2_IO, 0xef5);
mdelay(50);
cx_write(MO_GP2_IO, 0xcf7);
break;
default:
return -EINVAL;
}
return 0;
}
/* ----------------------------------------------------------------------- */ /* ----------------------------------------------------------------------- */
/* some DViCO specific stuff */ /* some DViCO specific stuff */
...@@ -2159,6 +2209,8 @@ static int cx88_xc2028_tuner_callback(void *priv, int command, int arg) ...@@ -2159,6 +2209,8 @@ static int cx88_xc2028_tuner_callback(void *priv, int command, int arg)
case CX88_BOARD_POWERCOLOR_REAL_ANGEL: case CX88_BOARD_POWERCOLOR_REAL_ANGEL:
case CX88_BOARD_GENIATECH_X8000_MT: case CX88_BOARD_GENIATECH_X8000_MT:
return cx88_xc3028_geniatech_tuner_callback(priv, command, arg); return cx88_xc3028_geniatech_tuner_callback(priv, command, arg);
case CX88_BOARD_PROLINK_PV_8000GT:
return cx88_pv_8000gt_callback(priv, command, arg);
case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO: case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
return cx88_dvico_xc2028_callback(priv, command, arg); return cx88_dvico_xc2028_callback(priv, command, arg);
} }
...@@ -2291,6 +2343,16 @@ static void cx88_card_setup_pre_i2c(struct cx88_core *core) ...@@ -2291,6 +2343,16 @@ static void cx88_card_setup_pre_i2c(struct cx88_core *core)
cx_set(MO_GP0_IO, 0x00000080); /* 702 out of reset */ cx_set(MO_GP0_IO, 0x00000080); /* 702 out of reset */
udelay(1000); udelay(1000);
break; break;
case CX88_BOARD_PROLINK_PV_8000GT:
cx_write(MO_GP2_IO, 0xcf7);
mdelay(50);
cx_write(MO_GP2_IO, 0xef5);
mdelay(50);
cx_write(MO_GP2_IO, 0xcf7);
msleep(10);
break;
case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
/* Enable the xc5000 tuner */ /* Enable the xc5000 tuner */
cx_set(MO_GP0_IO, 0x00001010); cx_set(MO_GP0_IO, 0x00001010);
......
...@@ -218,6 +218,7 @@ extern struct sram_channel cx88_sram_channels[]; ...@@ -218,6 +218,7 @@ extern struct sram_channel cx88_sram_channels[];
#define CX88_BOARD_GENIATECH_X8000_MT 63 #define CX88_BOARD_GENIATECH_X8000_MT 63
#define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO 64 #define CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO 64
#define CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD 65 #define CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD 65
#define CX88_BOARD_PROLINK_PV_8000GT 66
enum cx88_itype { enum cx88_itype {
CX88_VMUX_COMPOSITE1 = 1, CX88_VMUX_COMPOSITE1 = 1,
......
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