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Commit 24ff73a0 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'omap-for-v4.16/dt-clk-signed' of... 

Merge tag 'omap-for-v4.16/dt-clk-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Pull "Clock related dts changes for omaps for v4.16 merge window" from
Tony Lindgren:

This branch contains a series of dts changes from Tero Kristo to
start using clkctrl clocks.

Note that this branch is based on a merge of omap-for-v4.16/soc-signed
and an immutable commit from Tero Kristo fe7020e6 ("clk: ti: omap4:
clkctrl data fixes for opt-clocks") that is also in clk-next.

* tag 'omap-for-v4.16/dt-clk-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (57 commits)
  ARM: dts: dm816x: add clkctrl nodes
  ARM: dts: dm814x: add clkctrl nodes
  ARM: dts: am43xx: add clkctrl nodes
  ARM: dts: am33xx: add clkctrl nodes
  ARM: dts: dra7: add clkctrl nodes
  ARM: dts: omap5: add clkctrl nodes
  ARM: dts: omap4: add clkctrl nodes
  ARM: dts: dm816x: add bus functionality to base PRCM node
  ARM: dts: am43xx: add bus functionality to base PRCM node
  ARM: dts: am33xx: add bus functionality to base PRCM node
  ARM: dts: dra7: add bus functionality to base PRCM nodes
  ARM: dts: omap4: add bus functionality to base PRCM nodes
  ARM: dts: omap5: add bus functionality to base PRCM nodes
  ARM: dts: dm816x: add fck under timers1/2
  ARM: dts: dm814x: add fck under timers1/2
  ARM: dts: dra7: add fck under timer1
  ARM: dts: am43xx: add fck under timers1/2
  ARM: dts: am33xx: add fck under timers1/2
  ARM: dts: omap4: add fck under timer1
  ARM: dts: omap5: add fck under timer1
  ...
parents 8d7ac420 80a06c0d
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Showing with 3821 additions and 3187 deletions
arch/arm/boot/dts/am335x-bone-common.dtsi
View file @ 24ff73a0
......@@ -409,6 +409,6 @@ &sham {
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
arch/arm/boot/dts/am335x-boneblue.dts
View file @ 24ff73a0
......@@ -446,7 +446,7 @@ &sham {
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 24ff73a0
......@@ -790,6 +790,6 @@ &dcan1 {
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
arch/arm/boot/dts/am335x-evmsk.dts
View file @ 24ff73a0
......@@ -722,6 +722,6 @@ &lcdc {
};
&rtc {
clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
arch/arm/boot/dts/am33xx-clocks.dtsi
View file @ 24ff73a0
......@@ -292,14 +292,6 @@ dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
clock-div = <4>;
};
cefuse_fck: cefuse_fck@a20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <1>;
reg = <0x0a20>;
};
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
......@@ -316,14 +308,6 @@ clkdiv32k_ck: clkdiv32k_ck {
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick@14c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <1>;
reg = <0x014c>;
};
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
......@@ -350,49 +334,49 @@ mmu_fck: mmu_fck@914 {
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
......@@ -423,7 +407,7 @@ ieee5000_fck: ieee5000_fck@e4 {
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
......@@ -493,42 +477,10 @@ cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
gpio0_dbclk: gpio0_dbclk@408 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <18>;
reg = <0x0408>;
};
gpio1_dbclk: gpio1_dbclk@ac {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00ac>;
};
gpio2_dbclk: gpio2_dbclk@b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b0>;
};
gpio3_dbclk: gpio3_dbclk@b4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b4>;
};
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
......@@ -577,58 +529,6 @@ clkout2_div_ck: clkout2_div_ck@700 {
reg = <0x0700>;
};
dbg_sysclk_ck: dbg_sysclk_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <19>;
reg = <0x0414>;
};
dbg_clka_ck: dbg_clka_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <30>;
reg = <0x0414>;
};
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <22>;
reg = <0x0414>;
};
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <20>;
reg = <0x0414>;
};
stm_clk_div_ck: stm_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&stm_pmd_clock_mux_ck>;
ti,bit-shift = <27>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
trace_clk_div_ck: trace_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&trace_pmd_clk_mux_ck>;
ti,bit-shift = <24>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
......@@ -638,9 +538,88 @@ clkout2_ck: clkout2_ck@700 {
};
};
&prcm_clockdomains {
clk_24mhz_clkdm: clk_24mhz_clkdm {
compatible = "ti,clockdomain";
clocks = <&clkdiv32k_ick>;
&prcm {
l4_per_cm: l4_per_cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
l4_per_clkctrl: clk@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
};
arch/arm/boot/dts/am33xx.dtsi
View file @ 24ff73a0
......@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
......@@ -179,8 +180,11 @@ wkup_m3: wkup_m3@100000 {
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
......@@ -517,6 +521,8 @@ timer1: timer@44e31000 {
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
......@@ -524,6 +530,8 @@ timer2: timer@48040000 {
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
......@@ -571,7 +579,7 @@ rtc: rtc@44e3e000 {
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&clkdiv32k_ick>;
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
......@@ -1014,4 +1022,4 @@ rng: rng@48310000 {
};
};
/include/ "am33xx-clocks.dtsi"
#include "am33xx-clocks.dtsi"
arch/arm/boot/dts/am4372.dtsi
View file @ 24ff73a0
......@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>
/ {
compatible = "ti,am4372", "ti,am43";
......@@ -163,9 +164,12 @@ wkup_m3: wkup_m3@100000 {
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
......@@ -346,6 +350,8 @@ timer1: timer@44e31000 {
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
......@@ -353,6 +359,8 @@ timer2: timer@48040000 {
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
......@@ -993,7 +1001,7 @@ usb2_phy1: phy@483a8000 {
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
<&usb_otg_ss0_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
......@@ -1012,7 +1020,7 @@ usb2_phy2: phy@483e8000 {
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
<&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
......@@ -1175,4 +1183,4 @@ vpfe1: vpfe@48328000 {
};
};
/include/ "am43xx-clocks.dtsi"
#include "am43xx-clocks.dtsi"
arch/arm/boot/dts/am43x-epos-evm.dts
View file @ 24ff73a0
......@@ -985,7 +985,7 @@ &mcasp1 {
rx-num-evt = <32>;
};
&synctimer_32kclk {
&mux_synctimer32k_ck {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
arch/arm/boot/dts/am43xx-clocks.dtsi
View file @ 24ff73a0
......@@ -524,54 +524,6 @@ gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
reg = <0x4240>;
};
gpio0_dbclk: gpio0_dbclk@2b68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <8>;
reg = <0x2b68>;
};
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c78>;
};
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c80>;
};
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c88>;
};
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c90>;
};
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <8>;
reg = <0x8c98>;
};
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
......@@ -629,14 +581,6 @@ mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
reg = <0x4230>;
};
synctimer_32kclk: synctimer_32kclk@2a30 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&mux_synctimer32k_ck>;
ti,bit-shift = <8>;
reg = <0x2a30>;
};
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
......@@ -763,110 +707,76 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
ti,bit-shift = <8>;
reg = <0x2a48>;
};
};
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a60>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a68>;
};
clkout1_osc_div_ck: clkout1_osc_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
clkout1_src2_mux_ck: clkout1_src2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
clkout2_src_mux_ck: clkout2_src_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
reg = <0x4108>;
};
clkout2_pre_div_ck: clkout2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_src_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4108>;
};
clkout2_post_div_ck: clkout2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4108>;
};
clkout2_ck: clkout2_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout2_post_div_ck>;
ti,bit-shift = <16>;
reg = <0x4108>;
&prcm {
l4_wkup_cm: l4_wkup_cm@2800 {
compatible = "ti,omap4-cm";
reg = <0x2800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x400>;
l4_wkup_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x34c>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@8300 {
compatible = "ti,omap4-cm";
reg = <0x8300 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8300 0x100>;
mpu_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@8400 {
compatible = "ti,omap4-cm";
reg = <0x8400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8400 0x100>;
gfx_l3_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@8500 {
compatible = "ti,omap4-cm";
reg = <0x8500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
l4_rtc_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l4_per_cm: l4_per_cm@8800 {
compatible = "ti,omap4-cm";
reg = <0x8800 0xc00>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8800 0xc00>;
l4_per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0xb04>;
#clock-cells = <2>;
};
};
};
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View file @ 24ff73a0
......@@ -554,7 +554,7 @@ &pcie1_ep {
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";
......
arch/arm/boot/dts/dm814x-clocks.dtsi
View file @ 24ff73a0
......@@ -337,3 +337,33 @@ aud_clkin2_ck: aud_clkin2_ck {
clock-frequency = <20000000>;
};
};
&prcm {
default_cm: default_cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
default_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x5c>;
#clock-cells = <2>;
};
};
alwon_cm: alwon_cm@1400 {
compatible = "ti,omap4-cm";
reg = <0x1400 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x300>;
alwon_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x228>;
#clock-cells = <2>;
};
};
};
arch/arm/boot/dts/dm814x.dtsi
View file @ 24ff73a0
......@@ -250,6 +250,8 @@ timer1: timer@2e000 {
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
uart1: uart@20000 {
......@@ -287,6 +289,8 @@ timer2: timer@40000 {
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@42000 {
......
arch/arm/boot/dts/dm816x-clocks.dtsi
View file @ 24ff73a0
......@@ -248,3 +248,33 @@ timer7_fck: timer7_fck@3a8 {
reg = <0x03a8>;
};
};
&prcm {
default_cm: default_cm@500 {
compatible = "ti,omap4-cm";
reg = <0x500 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x500 0x100>;
default_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x5c>;
#clock-cells = <2>;
};
};
alwon_cm: alwon_cm@1400 {
compatible = "ti,omap4-cm";
reg = <0x1400 0x300>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x300>;
alwon_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x208>;
#clock-cells = <2>;
};
};
};
arch/arm/boot/dts/dm816x.dtsi
View file @ 24ff73a0
......@@ -67,8 +67,11 @@ ocp {
ranges;
prcm: prcm@48180000 {
compatible = "ti,dm816-prcm";
compatible = "ti,dm816-prcm", "simple-bus";
reg = <0x48180000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48180000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
......@@ -331,6 +334,8 @@ timer1: timer@4802e000 {
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
......@@ -338,6 +343,8 @@ timer2: timer@48040000 {
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
......
arch/arm/boot/dts/dra7-evm-common.dtsi
View file @ 24ff73a0
......@@ -204,7 +204,7 @@ &usb2 {
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
......@@ -222,7 +222,7 @@ atl2 {
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
......
arch/arm/boot/dts/dra7.dtsi
View file @ 24ff73a0
......@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
#include <dt-bindings/clock/dra7.h>
#define MAX_SOURCES 400
......@@ -224,8 +225,12 @@ edma_xbar: dma-router@c78 {
};
cm_core_aon: cm_core_aon@5000 {
compatible = "ti,dra7-cm-core-aon";
compatible = "ti,dra7-cm-core-aon",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x5000 0x2000>;
ranges = <0 0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
......@@ -237,8 +242,11 @@ cm_core_aon_clockdomains: clockdomains {
};
cm_core: cm_core@8000 {
compatible = "ti,dra7-cm-core";
compatible = "ti,dra7-cm-core", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8000 0x3000>;
ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
......@@ -263,9 +271,12 @@ counter32k: counter@4000 {
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
......@@ -876,6 +887,8 @@ timer1: timer@4ae18000 {
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
clock-names = "fck";
clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
};
timer2: timer@48032000 {
......@@ -1358,7 +1371,7 @@ qspi: qspi@4b300000 {
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
clocks = <&qspi_gfclk_div>;
clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1380,7 +1393,8 @@ sata_phy: phy@4A096000 {
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clocks = <&sys_clkin1>,
<&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
......@@ -1395,9 +1409,9 @@ pcie1_phy: pciephy@4a094000 {
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
<&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
......@@ -1415,9 +1429,9 @@ pcie2_phy: pciephy@4a095000 {
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
<&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
......@@ -1434,7 +1448,7 @@ sata: sata@4a141100 {
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
......@@ -1462,7 +1476,7 @@ usb2_phy1: phy@4a084000 {
reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
......@@ -1474,7 +1488,7 @@ usb2_phy2: phy@4a085000 {
reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
......@@ -1489,7 +1503,7 @@ usb3_phy1: phy@4a084400 {
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
<&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
......@@ -1636,7 +1650,7 @@ atl: atl@4843c000 {
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clock-names = "fck";
status = "disabled";
};
......@@ -1652,8 +1666,8 @@ mcasp1: mcasp@48460000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
<&mcasp1_ahclkr_mux>;
clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
<&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
......@@ -1669,8 +1683,9 @@ mcasp2: mcasp@48464000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
<&mcasp2_ahclkr_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
<&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
......@@ -1686,7 +1701,8 @@ mcasp3: mcasp@48468000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1702,7 +1718,8 @@ mcasp4: mcasp@4846c000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1718,7 +1735,8 @@ mcasp5: mcasp@48470000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1734,7 +1752,8 @@ mcasp6: mcasp@48474000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1750,7 +1769,8 @@ mcasp7: mcasp@48478000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1766,7 +1786,8 @@ mcasp8: mcasp@4847c000 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
<&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
......@@ -1788,7 +1809,7 @@ crossbar_mpu: crossbar@4a002a48 {
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
......@@ -1858,7 +1879,7 @@ dcan1: can@481cc000 {
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
status = "disabled";
};
......@@ -1889,7 +1910,7 @@ dispc@58001000 {
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
......@@ -1905,7 +1926,8 @@ hdmi: encoder@58060000 {
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
......@@ -2089,4 +2111,4 @@ &cpu_crit {
temperature = <120000>; /* milli Celsius */
};
/include/ "dra7xx-clocks.dtsi"
#include "dra7xx-clocks.dtsi"
arch/arm/boot/dts/dra72-evm-common.dtsi
View file @ 24ff73a0
......@@ -514,7 +514,7 @@ hdmi_out: endpoint {
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
......@@ -532,7 +532,7 @@ atl2 {
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
......
arch/arm/boot/dts/dra72x.dtsi
View file @ 24ff73a0
......@@ -25,8 +25,8 @@ &dss {
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_dss_clk>,
<&dss_video1_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk";
};
......
arch/arm/boot/dts/dra74x.dtsi
View file @ 24ff73a0
......@@ -93,9 +93,9 @@ &dss {
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
clocks = <&dss_dss_clk>,
<&dss_video1_clk>,
<&dss_video2_clk>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk";
};
......
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @ 24ff73a0
This diff is collapsed.
arch/arm/boot/dts/omap4.dtsi
View file @ 24ff73a0
......@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap4.h>
/ {
compatible = "ti,omap4430", "ti,omap4";
......@@ -143,8 +144,11 @@ l4_cfg: l4@4a000000 {
ranges = <0 0x4a000000 0x1000000>;
cm1: cm1@4000 {
compatible = "ti,omap4-cm1";
compatible = "ti,omap4-cm1", "simple-bus";
reg = <0x4000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
......@@ -156,8 +160,11 @@ cm1_clockdomains: clockdomains {
};
cm2: cm2@8000 {
compatible = "ti,omap4-cm2";
compatible = "ti,omap4-cm2", "simple-bus";
reg = <0x8000 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
......@@ -243,6 +250,9 @@ prm: prm@6000 {
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
......@@ -674,7 +684,7 @@ hsi: hsi@4a058000 {
reg-names = "sys", "gdd";
ti,hwmods = "hsi";
clocks = <&hsi_fck>;
clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
clock-names = "hsi_fck";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
......@@ -973,6 +983,8 @@ timer1: timer@4a318000 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
clock-names = "fck";
};
timer2: timer@48032000 {
......@@ -1202,7 +1214,7 @@ dss: dss@58000000 {
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
clocks = <&dss_dss_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
......@@ -1213,7 +1225,7 @@ dispc@58001000 {
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
......@@ -1222,7 +1234,7 @@ rfbi: encoder@58002000 {
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&dss_dss_clk>, <&l3_div_ck>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
......@@ -1231,7 +1243,7 @@ venc: encoder@58003000 {
reg = <0x58003000 0x1000>;
status = "disabled";
ti,hwmods = "dss_venc";
clocks = <&dss_tv_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
......@@ -1244,7 +1256,8 @@ dsi1: encoder@58004000 {
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
......@@ -1257,7 +1270,8 @@ dsi2: encoder@58005000 {
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
......@@ -1271,7 +1285,8 @@ hdmi: encoder@58006000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
......@@ -1280,4 +1295,4 @@ hdmi: encoder@58006000 {
};
};
/include/ "omap44xx-clocks.dtsi"
#include "omap44xx-clocks.dtsi"
arch/arm/boot/dts/omap44xx-clocks.dtsi
View file @ 24ff73a0
This diff is collapsed.
arch/arm/boot/dts/omap5.dtsi
View file @ 24ff73a0
......@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap5.h>
/ {
#address-cells = <2>;
......@@ -201,8 +202,12 @@ pbias_mmc_reg: pbias_mmc_omap5 {
};
cm_core_aon: cm_core_aon@4000 {
compatible = "ti,omap5-cm-core-aon";
compatible = "ti,omap5-cm-core-aon",
"simple-bus";
reg = <0x4000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
......@@ -214,8 +219,11 @@ cm_core_aon_clockdomains: clockdomains {
};
cm_core: cm_core@8000 {
compatible = "ti,omap5-cm-core";
compatible = "ti,omap5-cm-core", "simple-bus";
reg = <0x8000 0x3000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
......@@ -240,9 +248,12 @@ counter32k: counter@4000 {
};
prm: prm@6000 {
compatible = "ti,omap5-prm";
compatible = "ti,omap5-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
......@@ -734,6 +745,8 @@ timer1: timer@4ae18000 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
clock-names = "fck";
};
timer2: timer@48032000 {
......@@ -893,7 +906,8 @@ usb2_phy: usb2phy@4a084000 {
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
clocks = <&usb_phy_cm_clk32k>,
<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
};
......@@ -907,7 +921,7 @@ usb3_phy: usb3phy@4a084400 {
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
<&usb_otg_ss_refclk960m>;
<&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
......@@ -976,7 +990,8 @@ sata_phy: phy@4a096000 {
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin>, <&sata_ref_clk>;
clocks = <&sys_clkin>,
<&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};
......@@ -988,7 +1003,7 @@ sata: sata@4a141100 {
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
......@@ -998,7 +1013,7 @@ dss: dss@58000000 {
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
clocks = <&dss_dss_clk>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
......@@ -1009,7 +1024,7 @@ dispc@58001000 {
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_dss_clk>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
......@@ -1018,7 +1033,7 @@ rfbi: encoder@58002000 {
reg = <0x58002000 0x100>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&dss_dss_clk>, <&l3_iclk_div>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
clock-names = "fck", "ick";
};
......@@ -1031,7 +1046,8 @@ dsi1: encoder@58004000 {
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
......@@ -1044,7 +1060,8 @@ dsi2: encoder@58005000 {
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
clocks = <&dss_dss_clk>, <&dss_sys_clk>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
......@@ -1058,7 +1075,8 @@ hdmi: encoder@58060000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
......@@ -1132,7 +1150,7 @@ &cpu_thermal {
coefficients = <65 (-1791)>;
};
/include/ "omap54xx-clocks.dtsi"
#include "omap54xx-clocks.dtsi"
&gpu_thermal {
coefficients = <117 (-2992)>;
......
arch/arm/boot/dts/omap54xx-clocks.dtsi
View file @ 24ff73a0
This diff is collapsed.
arch/arm/mach-omap2/clockdomain.c
View file @ 24ff73a0
......@@ -1224,14 +1224,6 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
return 0;
}
u32 clkdm_xlate_address(struct clockdomain *clkdm)
{
if (arch_clkdm->clkdm_xlate_address)
return arch_clkdm->clkdm_xlate_address(clkdm);
return 0;
}
/**
* clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
* @clkdm: struct clockdomain *
......
arch/arm/mach-omap2/clockdomain.h
View file @ 24ff73a0
......@@ -175,7 +175,6 @@ struct clkdm_ops {
void (*clkdm_deny_idle)(struct clockdomain *clkdm);
int (*clkdm_clk_enable)(struct clockdomain *clkdm);
int (*clkdm_clk_disable)(struct clockdomain *clkdm);
u32 (*clkdm_xlate_address)(struct clockdomain *clkdm);
};
int clkdm_register_platform_funcs(struct clkdm_ops *co);
......@@ -214,7 +213,6 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
u32 clkdm_xlate_address(struct clockdomain *clkdm);
extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
......
arch/arm/mach-omap2/cm.h
View file @ 24ff73a0
......@@ -52,6 +52,7 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
* @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
* @module_enable: ptr to the SoC CM-specific module_enable impl
* @module_disable: ptr to the SoC CM-specific module_disable impl
* @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl
*/
struct cm_ll_data {
int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
......@@ -62,6 +63,7 @@ struct cm_ll_data {
u8 idlest_shift);
void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
};
extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
......@@ -72,8 +74,9 @@ int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
u8 idlest_shift);
int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(struct cm_ll_data *cld);
extern int cm_unregister(struct cm_ll_data *cld);
u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(const struct cm_ll_data *cld);
extern int cm_unregister(const struct cm_ll_data *cld);
int omap_cm_init(void);
int omap2_cm_base_init(void);
......
arch/arm/mach-omap2/cm2xxx.c
View file @ 24ff73a0
......@@ -385,7 +385,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
*
*/
static struct cm_ll_data omap2xxx_cm_ll_data = {
static const struct cm_ll_data omap2xxx_cm_ll_data = {
.split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
.wait_module_ready = &omap2xxx_cm_wait_module_ready,
};
......
arch/arm/mach-omap2/cm33xx.c
View file @ 24ff73a0
......@@ -333,6 +333,11 @@ static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
return 0;
}
static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset)
{
return cm_base.pa + inst + offset;
}
struct clkdm_ops am33xx_clkdm_operations = {
.clkdm_sleep = am33xx_clkdm_sleep,
.clkdm_wakeup = am33xx_clkdm_wakeup,
......@@ -342,11 +347,12 @@ struct clkdm_ops am33xx_clkdm_operations = {
.clkdm_clk_disable = am33xx_clkdm_clk_disable,
};
static struct cm_ll_data am33xx_cm_ll_data = {
static const struct cm_ll_data am33xx_cm_ll_data = {
.wait_module_ready = &am33xx_cm_wait_module_ready,
.wait_module_idle = &am33xx_cm_wait_module_idle,
.module_enable = &am33xx_cm_module_enable,
.module_disable = &am33xx_cm_module_disable,
.xlate_clkctrl = &am33xx_cm_xlate_clkctrl,
};
int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
......
arch/arm/mach-omap2/cm3xxx.c
View file @ 24ff73a0
......@@ -662,7 +662,7 @@ void omap3_cm_save_scratchpad_contents(u32 *ptr)
*
*/
static struct cm_ll_data omap3xxx_cm_ll_data = {
static const struct cm_ll_data omap3xxx_cm_ll_data = {
.split_idlest_reg = &omap3xxx_cm_split_idlest_reg,
.wait_module_ready = &omap3xxx_cm_wait_module_ready,
};
......
arch/arm/mach-omap2/cm_common.c
View file @ 24ff73a0
......@@ -29,7 +29,7 @@
* common CM functions
*/
static struct cm_ll_data null_cm_ll_data;
static struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
static const struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
/* cm_base: base virtual address of the CM IP block */
struct omap_domain_base cm_base;
......@@ -178,6 +178,16 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
return 0;
}
u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs)
{
if (!cm_ll_data->xlate_clkctrl) {
WARN_ONCE(1, "cm: %s: no low-level function defined\n",
__func__);
return 0;
}
return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs);
}
/**
* cm_register - register per-SoC low-level data with the CM
* @cld: low-level per-SoC OMAP CM data & function pointers to register
......@@ -189,7 +199,7 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
* is NULL, or -EEXIST if cm_register() has already been called
* without an intervening cm_unregister().
*/
int cm_register(struct cm_ll_data *cld)
int cm_register(const struct cm_ll_data *cld)
{
if (!cld)
return -EINVAL;
......@@ -213,7 +223,7 @@ int cm_register(struct cm_ll_data *cld)
* -EINVAL if @cld is NULL or if @cld does not match the struct
* cm_ll_data * previously registered by cm_register().
*/
int cm_unregister(struct cm_ll_data *cld)
int cm_unregister(const struct cm_ll_data *cld)
{
if (!cld || cm_ll_data != cld)
return -EINVAL;
......
arch/arm/mach-omap2/cminst44xx.c
View file @ 24ff73a0
......@@ -476,12 +476,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
return 0;
}
static u32 omap4_clkdm_xlate_address(struct clockdomain *clkdm)
static u32 omap4_cminst_xlate_clkctrl(u8 part, u16 inst, u16 offset)
{
u32 addr = _cm_bases[clkdm->prcm_partition].pa + clkdm->cm_inst +
clkdm->clkdm_offs;
return addr;
return _cm_bases[part].pa + inst + offset;
}
struct clkdm_ops omap4_clkdm_operations = {
......@@ -499,7 +496,6 @@ struct clkdm_ops omap4_clkdm_operations = {
.clkdm_deny_idle = omap4_clkdm_deny_idle,
.clkdm_clk_enable = omap4_clkdm_clk_enable,
.clkdm_clk_disable = omap4_clkdm_clk_disable,
.clkdm_xlate_address = omap4_clkdm_xlate_address,
};
struct clkdm_ops am43xx_clkdm_operations = {
......@@ -509,14 +505,14 @@ struct clkdm_ops am43xx_clkdm_operations = {
.clkdm_deny_idle = omap4_clkdm_deny_idle,
.clkdm_clk_enable = omap4_clkdm_clk_enable,
.clkdm_clk_disable = omap4_clkdm_clk_disable,
.clkdm_xlate_address = omap4_clkdm_xlate_address,
};
static struct cm_ll_data omap4xxx_cm_ll_data = {
static const struct cm_ll_data omap4xxx_cm_ll_data = {
.wait_module_ready = &omap4_cminst_wait_module_ready,
.wait_module_idle = &omap4_cminst_wait_module_idle,
.module_enable = &omap4_cminst_module_enable,
.module_disable = &omap4_cminst_module_disable,
.xlate_clkctrl = &omap4_cminst_xlate_clkctrl,
};
int __init omap4_cm_init(const struct omap_prcm_init_data *data)
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ 24ff73a0
......@@ -185,15 +185,15 @@
/**
* struct clkctrl_provider - clkctrl provider mapping data
* @addr: base address for the provider
* @offset: base offset for the provider
* @clkdm: base clockdomain for provider
* @size: size of the provider address space
* @offset: offset of the provider from PRCM instance base
* @node: device node associated with the provider
* @link: list link
*/
struct clkctrl_provider {
u32 addr;
u32 size;
u16 offset;
struct clockdomain *clkdm;
struct device_node *node;
struct list_head link;
};
......@@ -223,8 +223,7 @@ struct omap_hwmod_soc_ops {
void (*update_context_lost)(struct omap_hwmod *oh);
int (*get_context_lost)(struct omap_hwmod *oh);
int (*disable_direct_prcm)(struct omap_hwmod *oh);
u32 (*xlate_clkctrl)(struct omap_hwmod *oh,
struct clkctrl_provider *provider);
u32 (*xlate_clkctrl)(struct omap_hwmod *oh);
};
/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
......@@ -716,45 +715,28 @@ static const struct of_device_id ti_clkctrl_match_table[] __initconst = {
{ }
};
static int _match_clkdm(struct clockdomain *clkdm, void *user)
{
struct clkctrl_provider *provider = user;
if (clkdm_xlate_address(clkdm) == provider->addr) {
pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__,
clkdm->name, provider->addr,
provider->node->parent->name);
provider->clkdm = clkdm;
return -1;
}
return 0;
}
static int _setup_clkctrl_provider(struct device_node *np)
{
const __be32 *addrp;
struct clkctrl_provider *provider;
u64 size;
provider = memblock_virt_alloc(sizeof(*provider), 0);
if (!provider)
return -ENOMEM;
addrp = of_get_address(np, 0, NULL, NULL);
addrp = of_get_address(np, 0, &size, NULL);
provider->addr = (u32)of_translate_address(np, addrp);
provider->offset = provider->addr & 0xff;
addrp = of_get_address(np->parent, 0, NULL, NULL);
provider->offset = provider->addr -
(u32)of_translate_address(np->parent, addrp);
provider->addr &= ~0xff;
provider->size = size | 0xff;
provider->node = np;
clkdm_for_each(_match_clkdm, provider);
if (!provider->clkdm) {
pr_err("%s: nothing matched for node %s (%x)\n",
__func__, np->parent->name, provider->addr);
memblock_free_early(__pa(provider), sizeof(*provider));
return -EINVAL;
}
pr_debug("%s: %s: %x...%x [+%x]\n", __func__, np->parent->name,
provider->addr, provider->addr + provider->size,
provider->offset);
list_add(&provider->link, &clkctrl_providers);
......@@ -775,32 +757,48 @@ static int _init_clkctrl_providers(void)
return ret;
}
static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh,
struct clkctrl_provider *provider)
static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh)
{
return oh->prcm.omap4.clkctrl_offs -
provider->offset - provider->clkdm->clkdm_offs;
if (!oh->prcm.omap4.modulemode)
return 0;
return omap_cm_xlate_clkctrl(oh->clkdm->prcm_partition,
oh->clkdm->cm_inst,
oh->prcm.omap4.clkctrl_offs);
}
static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh)
{
struct clkctrl_provider *provider;
struct clk *clk;
u32 addr;
if (!soc_ops.xlate_clkctrl)
return NULL;
addr = soc_ops.xlate_clkctrl(oh);
if (!addr)
return NULL;
pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr);
list_for_each_entry(provider, &clkctrl_providers, link) {
if (provider->clkdm == oh->clkdm) {
if (provider->addr <= addr &&
provider->addr + provider->size >= addr) {
struct of_phandle_args clkspec;
clkspec.np = provider->node;
clkspec.args_count = 2;
clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider);
clkspec.args[0] = addr - provider->addr -
provider->offset;
clkspec.args[1] = 0;
clk = of_clk_get_from_provider(&clkspec);
pr_debug("%s: %s got %p (offset=%x, provider=%s)\n",
__func__, oh->name, clk, clkspec.args[0],
provider->node->parent->name);
return clk;
}
}
......@@ -3521,6 +3519,7 @@ void __init omap_hwmod_init(void)
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
soc_ops.init_clkdm = _init_clkdm;
soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl;
} else {
WARN(1, "omap_hwmod: unknown SoC type\n");
}
......
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View file @ 24ff73a0
......@@ -988,7 +988,7 @@ static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
static struct omap_hwmod dm81xx_sata_hwmod = {
.name = "sata",
.clkdm_name = "default_sata_clkdm",
.clkdm_name = "default_clkdm",
.flags = HWMOD_NO_IDLEST,
.prcm = {
.omap4 = {
......
drivers/clk/ti/apll.c
View file @ 24ff73a0
......@@ -133,9 +133,10 @@ static const struct clk_ops apll_ck_ops = {
.get_parent = &dra7_init_apll_parent,
};
static void __init omap_clk_register_apll(struct clk_hw *hw,
static void __init omap_clk_register_apll(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data;
struct clk *clk;
......
drivers/clk/ti/clk-33xx.c
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drivers/clk/ti/clk-3xxx.c
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drivers/clk/ti/clk-43xx.c
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drivers/clk/ti/clk-44xx.c
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drivers/clk/ti/clk-54xx.c
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drivers/clk/ti/clk-7xx.c
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drivers/clk/ti/clk-814x.c
View file @ 24ff73a0
......@@ -9,23 +9,48 @@
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <linux/of_platform.h>
#include <dt-bindings/clock/dm814.h>
#include "clock.h"
static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
{ DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
{ DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
{ DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
{ DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
{ DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
{ DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
{ DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
{ DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
{ 0 },
};
const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
{ 0x48180500, dm814_default_clkctrl_regs },
{ 0x48181400, dm814_alwon_clkctrl_regs },
{ 0 },
};
static struct ti_dt_clk dm814_clks[] = {
DT_CLK(NULL, "devosc_ck", "devosc_ck"),
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
{ .node_name = NULL },
};
......@@ -83,6 +108,7 @@ int __init dm814x_dt_clk_init(void)
{
ti_dt_clocks_register(dm814_clks);
omap2_clk_disable_autoidle_all();
ti_clk_add_aliases();
omap2_clk_enable_init_clocks(NULL, 0);
timer_clocks_initialized = true;
......
drivers/clk/ti/clk-816x.c
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drivers/clk/ti/clk.c
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drivers/clk/ti/clkctrl.c
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drivers/clk/ti/clock.h
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drivers/clk/ti/composite.c
View file @ 24ff73a0
......@@ -161,9 +161,10 @@ struct clk *ti_clk_register_composite(struct ti_clk *setup)
}
#endif
static void __init _register_composite(struct clk_hw *hw,
static void __init _register_composite(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk *clk;
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
struct component_clk *comp;
......
drivers/clk/ti/dpll.c
View file @ 24ff73a0
......@@ -152,9 +152,10 @@ static const struct clk_ops dpll_x2_ck_ops = {
* clk-bypass is missing), the clock is added to retry list and
* the initialization is retried on later stage.
*/
static void __init _register_dpll(struct clk_hw *hw,
static void __init _register_dpll(void *user,
struct device_node *node)
{
struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data;
struct clk *clk;
......
include/dt-bindings/clock/am3.h 0 → 100644
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include/dt-bindings/clock/am4.h 0 → 100644
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include/dt-bindings/clock/dm814.h 0 → 100644
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include/dt-bindings/clock/dm816.h 0 → 100644
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include/dt-bindings/clock/dra7.h 0 → 100644
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This diff is collapsed.
include/dt-bindings/clock/omap5.h 0 → 100644
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