Commit 2981795c authored by Martyn Welch's avatar Martyn Welch Committed by Greg Kroah-Hartman

vme: tsi148: CR/CSR logic arround the wrong way

The logic in the init routine for the TSI148 is inverted. It isn't switching
on the CR/CSR space when it should be and is reporting it's on when its not.

Correct the logic to do the right thing.
Reported-by: default avatarDe Roo, Steven <steven.deroo@arcelormittal.com>
Signed-off-by: default avatarMartyn Welch <martyn.welch@ge.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e31c51e4
...@@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, ...@@ -2300,12 +2300,13 @@ static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
if (crat & TSI148_LCSR_CRAT_EN) { if (crat & TSI148_LCSR_CRAT_EN)
dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
else {
dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
iowrite32be(crat | TSI148_LCSR_CRAT_EN, iowrite32be(crat | TSI148_LCSR_CRAT_EN,
bridge->base + TSI148_LCSR_CRAT); bridge->base + TSI148_LCSR_CRAT);
} else }
dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
/* If we want flushed, error-checked writes, set up a window /* If we want flushed, error-checked writes, set up a window
* over the CR/CSR registers. We read from here to safely flush * over the CR/CSR registers. We read from here to safely flush
......
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