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Commit 3155f7f2 authored by Kumar Gala's avatar Kumar Gala
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[PPC] Remove 83xx from arch/ppc 

83xx exists in arch/powerpc as well as cuImage support to boot from
a u-boot that doesn't support device trees.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 80f4ec7f
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Showing with 15 additions and 3097 deletions
arch/ppc/Kconfig
View file @ 3155f7f2
......@@ -78,18 +78,18 @@ choice
default 6xx
config 6xx
bool "6xx/7xx/74xx/52xx/82xx/83xx"
bool "6xx/7xx/74xx/52xx/82xx"
select PPC_FPU
help
There are four types of PowerPC chips supported. The more common
types (601, 603, 604, 740, 750, 7400), the older Freescale
(formerly Motorola) embedded versions (821, 823, 850, 855, 860,
52xx, 82xx, 83xx), the IBM embedded versions (403 and 405) and
52xx, 82xx), the IBM embedded versions (403 and 405) and
the Book E embedded processors from IBM (44x) and Freescale (85xx).
For support for 64-bit processors, set ARCH=powerpc.
Unless you are building a kernel for one of the embedded processor
systems, choose 6xx.
Also note that because the 52xx, 82xx, & 83xx family have a 603e
Also note that because the 52xx, 82xx family have a 603e
core, specific support for that chipset is asked later on.
config 40x
......@@ -153,7 +153,7 @@ config PHYS_64BIT
config ALTIVEC
bool "AltiVec Support"
depends on 6xx
depends on !8260 && !83xx
depends on !8260
---help---
This option enables kernel support for the Altivec extensions to the
PowerPC processor. The kernel currently supports saving and restoring
......@@ -184,7 +184,7 @@ config SPE
config TAU
bool "Thermal Management Support"
depends on 6xx && !8260 && !83xx
depends on 6xx && !8260
help
G3 and G4 processors have an on-chip temperature sensor called the
'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
......@@ -721,16 +721,6 @@ config LITE5200B
Support for the LITE5200B dev board for the MPC5200 from Freescale.
This is the new board with 2 PCI slots.
config MPC834x_SYS
bool "Freescale MPC834x SYS"
help
This option enables support for the MPC 834x SYS evaluation board.
Be aware that PCI buses can only function when SYS board is plugged
into the PIB (Platform IO Board) board from Freescale which provide
3 PCI slots. The PIBs PCI initialization is the bootloader's
responsibility.
config EV64360
bool "Marvell-EV64360BP"
help
......@@ -774,18 +764,6 @@ config 8272
The MPC8272 CPM has a different internal dpram setup than other CPM2
devices
config 83xx
bool
default y if MPC834x_SYS
config MPC834x
bool
default y if MPC834x_SYS
config PPC_83xx
bool
default y if 83xx
config CPM1
bool
depends on 8xx
......@@ -811,8 +789,7 @@ config PPC_GEN550
bool
depends on SANDPOINT || SPRUCE || PPLUS || \
PRPMC750 || PRPMC800 || LOPEC || \
(EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \
83xx
(EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D
default y
config FORCE
......@@ -1074,7 +1051,7 @@ config PPC_I8259
config PPC_INDIRECT_PCI
bool
depends on PCI
default y if 40x || 44x || 85xx || 83xx || PPC_PREP
default y if 40x || 44x || 85xx || PPC_PREP
default n
config EISA
......@@ -1091,8 +1068,8 @@ config MCA
bool
config PCI
bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx
default y if !40x && !CPM2 && !8xx && !83xx && !85xx
bool "PCI support" if 40x || CPM2 || 85xx || PPC_MPC52xx
default y if !40x && !CPM2 && !8xx && !85xx
default PCI_QSPAN if !4xx && !CPM2 && 8xx
help
Find out whether your system includes a PCI bus. PCI is the name of
......@@ -1106,11 +1083,6 @@ config PCI_DOMAINS
config PCI_SYSCALL
def_bool PCI
config MPC83xx_PCI2
bool "Support for 2nd PCI host controller"
depends on PCI && MPC834x
default y if MPC834x_SYS
config PCI_QSPAN
bool "QSpan PCI"
depends on !4xx && !CPM2 && 8xx
......
arch/ppc/Makefile
View file @ 3155f7f2
......@@ -65,7 +65,6 @@ core-y += arch/ppc/kernel/ arch/powerpc/kernel/ \
arch/ppc/syslib/ arch/powerpc/sysdev/ \
arch/powerpc/lib/
core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/
core-$(CONFIG_83xx) += arch/ppc/platforms/83xx/
core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/
core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/
core-$(CONFIG_XMON) += arch/ppc/xmon/
......
arch/ppc/configs/mpc834x_sys_defconfig deleted 100644 → 0
View file @ 80f4ec7f
This diff is collapsed.
arch/ppc/kernel/ppc_ksyms.c
View file @ 3155f7f2
......@@ -244,8 +244,7 @@ EXPORT_SYMBOL(debugger_fault_handler);
EXPORT_SYMBOL(cpm_install_handler);
EXPORT_SYMBOL(cpm_free_handler);
#endif /* CONFIG_8xx */
#if defined(CONFIG_8xx) || defined(CONFIG_40x) || defined(CONFIG_85xx) ||\
defined(CONFIG_83xx)
#if defined(CONFIG_8xx) || defined(CONFIG_40x) || defined(CONFIG_85xx)
EXPORT_SYMBOL(__res);
#endif
......
arch/ppc/kernel/setup.c
View file @ 3155f7f2
......@@ -38,7 +38,7 @@
#include <asm/xmon.h>
#include <asm/ocp.h>
#define USES_PPC_SYS (defined(CONFIG_85xx) || defined(CONFIG_83xx) || \
#define USES_PPC_SYS (defined(CONFIG_85xx) || \
defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_8260) || \
defined(CONFIG_PPC_MPC52xx))
......
arch/ppc/mm/mmu_context.c
View file @ 3155f7f2
......@@ -2,7 +2,7 @@
* This file contains the routines for handling the MMU on those
* PowerPC implementations where the MMU substantially follows the
* architecture specification. This includes the 6xx, 7xx, 7xxx,
* 8260, and 83xx implementations but excludes the 8xx and 4xx.
* and 8260 implementations but excludes the 8xx and 4xx.
* -- paulus
*
* Derived from arch/ppc/mm/init.c:
......
arch/ppc/mm/ppc_mmu.c
View file @ 3155f7f2
......@@ -2,7 +2,7 @@
* This file contains the routines for handling the MMU on those
* PowerPC implementations where the MMU substantially follows the
* architecture specification. This includes the 6xx, 7xx, 7xxx,
* 8260, and 83xx implementations but excludes the 8xx and 4xx.
* and 8260 implementations but excludes the 8xx and 4xx.
* -- paulus
*
* Derived from arch/ppc/mm/init.c:
......
arch/ppc/platforms/83xx/Makefile deleted 100644 → 0
View file @ 80f4ec7f
#
# Makefile for the PowerPC 83xx linux kernel.
#
obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o
arch/ppc/platforms/83xx/mpc834x_sys.c deleted 100644 → 0
View file @ 80f4ec7f
/*
* MPC834x SYS board specific routines
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/serial.h>
#include <linux/tty.h> /* for linux/serial_core.h */
#include <linux/serial_core.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/fsl_devices.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ipic.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc83xx.h>
#include <asm/irq.h>
#include <asm/kgdb.h>
#include <asm/ppc_sys.h>
#include <mm/mmu_decl.h>
#include <syslib/ppc83xx_setup.h>
#ifndef CONFIG_PCI
unsigned long isa_io_base = 0;
unsigned long isa_mem_base = 0;
#endif
extern unsigned long total_memory; /* in mm/init */
unsigned char __res[sizeof (bd_t)];
#ifdef CONFIG_PCI
int
mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
{PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
{PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
{0, 0, 0, 0},
{PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
{PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
{PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
{PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
{0, 0, 0, 0}, /* idsel 0x19 */
{0, 0, 0, 0}, /* idsel 0x20 */
};
const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
int
mpc83xx_exclude_device(u_char bus, u_char devfn)
{
return PCIBIOS_SUCCESSFUL;
}
#endif /* CONFIG_PCI */
/* ************************************************************************
*
* Setup the architecture
*
*/
static void __init
mpc834x_sys_setup_arch(void)
{
bd_t *binfo = (bd_t *) __res;
unsigned int freq;
struct gianfar_platform_data *pdata;
struct gianfar_mdio_data *mdata;
/* get the core frequency */
freq = binfo->bi_intfreq;
/* Set loops_per_jiffy to a half-way reasonable value,
for use until calibrate_delay gets called. */
loops_per_jiffy = freq / HZ;
#ifdef CONFIG_PCI
/* setup PCI host bridges */
mpc83xx_setup_hose();
#endif
mpc83xx_early_serial_map();
/* setup the board related info for the MDIO bus */
mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC83xx_MDIO);
mdata->irq[0] = MPC83xx_IRQ_EXT1;
mdata->irq[1] = MPC83xx_IRQ_EXT2;
mdata->irq[2] = PHY_POLL;
mdata->irq[31] = PHY_POLL;
/* setup the board related information for the enet controllers */
pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
if (pdata) {
pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
pdata->bus_id = 0;
pdata->phy_id = 0;
memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
}
pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
if (pdata) {
pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
pdata->bus_id = 0;
pdata->phy_id = 1;
memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
}
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
}
static void __init
mpc834x_sys_map_io(void)
{
/* we steal the lowest ioremap addr for virt space */
io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
}
int
mpc834x_sys_show_cpuinfo(struct seq_file *m)
{
uint pvid, svid, phid1;
bd_t *binfo = (bd_t *) __res;
unsigned int freq;
/* get the core frequency */
freq = binfo->bi_intfreq;
pvid = mfspr(SPRN_PVR);
svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "core clock\t: %d MHz\n"
"bus clock\t: %d MHz\n",
(int)(binfo->bi_intfreq / 1000000),
(int)(binfo->bi_busfreq / 1000000));
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
/* Display cpu Pll setting */
phid1 = mfspr(SPRN_HID1);
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
/* Display the amount of memory */
seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024)));
return 0;
}
void __init
mpc834x_sys_init_IRQ(void)
{
bd_t *binfo = (bd_t *) __res;
u8 senses[8] = {
0, /* EXT 0 */
IRQ_SENSE_LEVEL, /* EXT 1 */
IRQ_SENSE_LEVEL, /* EXT 2 */
0, /* EXT 3 */
#ifdef CONFIG_PCI
IRQ_SENSE_LEVEL, /* EXT 4 */
IRQ_SENSE_LEVEL, /* EXT 5 */
IRQ_SENSE_LEVEL, /* EXT 6 */
IRQ_SENSE_LEVEL, /* EXT 7 */
#else
0, /* EXT 4 */
0, /* EXT 5 */
0, /* EXT 6 */
0, /* EXT 7 */
#endif
};
ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
*/
ipic_set_default_priority();
}
#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
extern ulong ds1374_get_rtc_time(void);
extern int ds1374_set_rtc_time(ulong);
static int __init
mpc834x_rtc_hookup(void)
{
struct timespec tv;
ppc_md.get_rtc_time = ds1374_get_rtc_time;
ppc_md.set_rtc_time = ds1374_set_rtc_time;
tv.tv_nsec = 0;
tv.tv_sec = (ppc_md.get_rtc_time)();
do_settimeofday(&tv);
return 0;
}
late_initcall(mpc834x_rtc_hookup);
#endif
static __inline__ void
mpc834x_sys_set_bat(void)
{
/* we steal the lowest ioremap addr for virt space */
mb();
mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e);
mtspr(SPRN_DBAT1L, immrbar | 0x2a);
mb();
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
bd_t *binfo = (bd_t *) __res;
/* parse_bootinfo must always be called first */
parse_bootinfo(find_bootinfo());
/*
* If we were passed in a board information, copy it into the
* residual data area.
*/
if (r3) {
memcpy((void *) __res, (void *) (r3 + KERNELBASE),
sizeof (bd_t));
}
#if defined(CONFIG_BLK_DEV_INITRD)
/*
* If the init RAM disk has been configured in, and there's a valid
* starting address for it, set it up.
*/
if (r4) {
initrd_start = r4 + KERNELBASE;
initrd_end = r5 + KERNELBASE;
}
#endif /* CONFIG_BLK_DEV_INITRD */
/* Copy the kernel command line arguments to a safe place. */
if (r6) {
*(char *) (r7 + KERNELBASE) = 0;
strcpy(cmd_line, (char *) (r6 + KERNELBASE));
}
immrbar = binfo->bi_immr_base;
mpc834x_sys_set_bat();
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
{
struct uart_port p;
memset(&p, 0, sizeof (p));
p.iotype = UPIO_MEM;
p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
p.uartclk = binfo->bi_busfreq;
gen550_init(0, &p);
memset(&p, 0, sizeof (p));
p.iotype = UPIO_MEM;
p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
p.uartclk = binfo->bi_busfreq;
gen550_init(1, &p);
}
#endif
identify_ppc_sys_by_id(mfspr(SPRN_SVR));
/* setup the PowerPC module struct */
ppc_md.setup_arch = mpc834x_sys_setup_arch;
ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo;
ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
ppc_md.get_irq = ipic_get_irq;
ppc_md.restart = mpc83xx_restart;
ppc_md.power_off = mpc83xx_power_off;
ppc_md.halt = mpc83xx_halt;
ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory;
ppc_md.setup_io_mappings = mpc834x_sys_map_io;
ppc_md.time_init = mpc83xx_time_init;
ppc_md.set_rtc_time = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.calibrate_decr = mpc83xx_calibrate_decr;
ppc_md.early_serial_map = mpc83xx_early_serial_map;
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
if (ppc_md.progress)
ppc_md.progress("mpc834x_sys_init(): exit", 0);
return;
}
arch/ppc/platforms/83xx/mpc834x_sys.h deleted 100644 → 0
View file @ 80f4ec7f
/*
* MPC834X SYS common board definitions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MACH_MPC83XX_SYS_H__
#define __MACH_MPC83XX_SYS_H__
#include <linux/init.h>
#include <syslib/ppc83xx_setup.h>
#include <asm/ppcboot.h>
#define VIRT_IMMRBAR ((uint)0xfe000000)
#define BCSR_PHYS_ADDR ((uint)0xf8000000)
#define BCSR_SIZE ((uint)(32 * 1024))
#define BCSR_MISC_REG2_OFF 0x07
#define BCSR_MISC_REG2_PORESET 0x01
#define BCSR_MISC_REG3_OFF 0x08
#define BCSR_MISC_REG3_CNFLOCK 0x80
#define PIRQA MPC83xx_IRQ_EXT4
#define PIRQB MPC83xx_IRQ_EXT5
#define PIRQC MPC83xx_IRQ_EXT6
#define PIRQD MPC83xx_IRQ_EXT7
#define MPC83xx_PCI1_LOWER_IO 0x00000000
#define MPC83xx_PCI1_UPPER_IO 0x00ffffff
#define MPC83xx_PCI1_LOWER_MEM 0x80000000
#define MPC83xx_PCI1_UPPER_MEM 0x9fffffff
#define MPC83xx_PCI1_IO_BASE 0xe2000000
#define MPC83xx_PCI1_MEM_OFFSET 0x00000000
#define MPC83xx_PCI1_IO_SIZE 0x01000000
#define MPC83xx_PCI2_LOWER_IO 0x00000000
#define MPC83xx_PCI2_UPPER_IO 0x00ffffff
#define MPC83xx_PCI2_LOWER_MEM 0xa0000000
#define MPC83xx_PCI2_UPPER_MEM 0xbfffffff
#define MPC83xx_PCI2_IO_BASE 0xe3000000
#define MPC83xx_PCI2_MEM_OFFSET 0x00000000
#define MPC83xx_PCI2_IO_SIZE 0x01000000
#endif /* __MACH_MPC83XX_SYS_H__ */
arch/ppc/syslib/Makefile
View file @ 3155f7f2
......@@ -93,11 +93,6 @@ obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
ifeq ($(CONFIG_85xx),y)
obj-$(CONFIG_PCI) += pci_auto.o
endif
obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
mpc83xx_sys.o mpc83xx_devices.o ipic.o
ifeq ($(CONFIG_83xx),y)
obj-$(CONFIG_PCI) += pci_auto.o
endif
obj-$(CONFIG_MPC8548_CDS) += todc_time.o
obj-$(CONFIG_MPC8555_CDS) += todc_time.o
obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
......
arch/ppc/syslib/ipic.c deleted 100644 → 0
View file @ 80f4ec7f
This diff is collapsed.
arch/ppc/syslib/ipic.h deleted 100644 → 0
View file @ 80f4ec7f
/*
* IPIC private definitions and structure.
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __IPIC_H__
#define __IPIC_H__
#include <asm/ipic.h>
#define MPC83xx_IPIC_SIZE (0x00100)
/* System Global Interrupt Configuration Register */
#define SICFR_IPSA 0x00010000
#define SICFR_IPSD 0x00080000
#define SICFR_MPSA 0x00200000
#define SICFR_MPSB 0x00400000
/* System External Interrupt Mask Register */
#define SEMSR_SIRQ0 0x00008000
/* System Error Control Register */
#define SERCR_MCPR 0x00000001
struct ipic {
volatile u32 __iomem *regs;
unsigned int irq_offset;
};
struct ipic_info {
u8 pend; /* pending register offset from base */
u8 mask; /* mask register offset from base */
u8 prio; /* priority register offset from base */
u8 force; /* force register offset from base */
u8 bit; /* register bit position (as per doc)
bit mask = 1 << (31 - bit) */
u8 prio_mask; /* priority mask value */
};
#endif /* __IPIC_H__ */
arch/ppc/syslib/mpc83xx_devices.c deleted 100644 → 0
View file @ 80f4ec7f
/*
* MPC83xx Device descriptions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/serial_8250.h>
#include <linux/fsl_devices.h>
#include <asm/mpc83xx.h>
#include <asm/irq.h>
#include <asm/ppc_sys.h>
#include <asm/machdep.h>
/* We use offsets for IORESOURCE_MEM since we do not know at compile time
* what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup
*/
struct gianfar_mdio_data mpc83xx_mdio_pdata = {
};
static struct gianfar_platform_data mpc83xx_tsec1_pdata = {
.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
FSL_GIANFAR_DEV_HAS_MULTI_INTR,
};
static struct gianfar_platform_data mpc83xx_tsec2_pdata = {
.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
FSL_GIANFAR_DEV_HAS_MULTI_INTR,
};
static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = {
.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
};
static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = {
.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
};
static struct plat_serial8250_port serial_platform_data[] = {
[0] = {
.mapbase = 0x4500,
.irq = MPC83xx_IRQ_UART1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
[1] = {
.mapbase = 0x4600,
.irq = MPC83xx_IRQ_UART2,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{ },
};
struct platform_device ppc_sys_platform_devices[] = {
[MPC83xx_TSEC1] = {
.name = "fsl-gianfar",
.id = 1,
.dev.platform_data = &mpc83xx_tsec1_pdata,
.num_resources = 4,
.resource = (struct resource[]) {
{
.start = 0x24000,
.end = 0x24fff,
.flags = IORESOURCE_MEM,
},
{
.name = "tx",
.start = MPC83xx_IRQ_TSEC1_TX,
.end = MPC83xx_IRQ_TSEC1_TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = MPC83xx_IRQ_TSEC1_RX,
.end = MPC83xx_IRQ_TSEC1_RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "error",
.start = MPC83xx_IRQ_TSEC1_ERROR,
.end = MPC83xx_IRQ_TSEC1_ERROR,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_TSEC2] = {
.name = "fsl-gianfar",
.id = 2,
.dev.platform_data = &mpc83xx_tsec2_pdata,
.num_resources = 4,
.resource = (struct resource[]) {
{
.start = 0x25000,
.end = 0x25fff,
.flags = IORESOURCE_MEM,
},
{
.name = "tx",
.start = MPC83xx_IRQ_TSEC2_TX,
.end = MPC83xx_IRQ_TSEC2_TX,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = MPC83xx_IRQ_TSEC2_RX,
.end = MPC83xx_IRQ_TSEC2_RX,
.flags = IORESOURCE_IRQ,
},
{
.name = "error",
.start = MPC83xx_IRQ_TSEC2_ERROR,
.end = MPC83xx_IRQ_TSEC2_ERROR,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_IIC1] = {
.name = "fsl-i2c",
.id = 1,
.dev.platform_data = &mpc83xx_fsl_i2c1_pdata,
.num_resources = 2,
.resource = (struct resource[]) {
{
.start = 0x3000,
.end = 0x30ff,
.flags = IORESOURCE_MEM,
},
{
.start = MPC83xx_IRQ_IIC1,
.end = MPC83xx_IRQ_IIC1,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_IIC2] = {
.name = "fsl-i2c",
.id = 2,
.dev.platform_data = &mpc83xx_fsl_i2c2_pdata,
.num_resources = 2,
.resource = (struct resource[]) {
{
.start = 0x3100,
.end = 0x31ff,
.flags = IORESOURCE_MEM,
},
{
.start = MPC83xx_IRQ_IIC2,
.end = MPC83xx_IRQ_IIC2,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_DUART] = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = serial_platform_data,
},
[MPC83xx_SEC2] = {
.name = "fsl-sec2",
.id = 1,
.num_resources = 2,
.resource = (struct resource[]) {
{
.start = 0x30000,
.end = 0x3ffff,
.flags = IORESOURCE_MEM,
},
{
.start = MPC83xx_IRQ_SEC2,
.end = MPC83xx_IRQ_SEC2,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_USB2_DR] = {
.name = "fsl-ehci",
.id = 1,
.num_resources = 2,
.resource = (struct resource[]) {
{
.start = 0x23000,
.end = 0x23fff,
.flags = IORESOURCE_MEM,
},
{
.start = MPC83xx_IRQ_USB2_DR,
.end = MPC83xx_IRQ_USB2_DR,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_USB2_MPH] = {
.name = "fsl-ehci",
.id = 2,
.num_resources = 2,
.resource = (struct resource[]) {
{
.start = 0x22000,
.end = 0x22fff,
.flags = IORESOURCE_MEM,
},
{
.start = MPC83xx_IRQ_USB2_MPH,
.end = MPC83xx_IRQ_USB2_MPH,
.flags = IORESOURCE_IRQ,
},
},
},
[MPC83xx_MDIO] = {
.name = "fsl-gianfar_mdio",
.id = 0,
.dev.platform_data = &mpc83xx_mdio_pdata,
.num_resources = 1,
.resource = (struct resource[]) {
{
.start = 0x24520,
.end = 0x2453f,
.flags = IORESOURCE_MEM,
},
},
},
};
static int __init mach_mpc83xx_fixup(struct platform_device *pdev)
{
ppc_sys_fixup_mem_resource(pdev, immrbar);
return 0;
}
static int __init mach_mpc83xx_init(void)
{
if (ppc_md.progress)
ppc_md.progress("mach_mpc83xx_init:enter", 0);
ppc_sys_device_fixup = mach_mpc83xx_fixup;
return 0;
}
postcore_initcall(mach_mpc83xx_init);
arch/ppc/syslib/mpc83xx_sys.c deleted 100644 → 0
View file @ 80f4ec7f
/*
* MPC83xx System descriptions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <asm/ppc_sys.h>
struct ppc_sys_spec *cur_ppc_sys_spec;
struct ppc_sys_spec ppc_sys_specs[] = {
{
.ppc_sys_name = "8349E",
.mask = 0xFFFF0000,
.value = 0x80500000,
.num_devices = 9,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8349",
.mask = 0xFFFF0000,
.value = 0x80510000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8347E",
.mask = 0xFFFF0000,
.value = 0x80520000,
.num_devices = 9,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8347",
.mask = 0xFFFF0000,
.value = 0x80530000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8347E",
.mask = 0xFFFF0000,
.value = 0x80540000,
.num_devices = 9,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8347",
.mask = 0xFFFF0000,
.value = 0x80550000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART,
MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8343E",
.mask = 0xFFFF0000,
.value = 0x80560000,
.num_devices = 8,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2,
MPC83xx_USB2_DR, MPC83xx_MDIO
},
},
{
.ppc_sys_name = "8343",
.mask = 0xFFFF0000,
.value = 0x80570000,
.num_devices = 7,
.device_list = (enum ppc_sys_devices[])
{
MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1,
MPC83xx_IIC2, MPC83xx_DUART,
MPC83xx_USB2_DR, MPC83xx_MDIO
},
},
{ /* default match */
.ppc_sys_name = "",
.mask = 0x00000000,
.value = 0x00000000,
},
};
arch/ppc/syslib/ppc83xx_pci.h deleted 100644 → 0
View file @ 80f4ec7f
/* Created by Tony Li <tony.li@freescale.com>
* Copyright (c) 2005 freescale semiconductor
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
#define __PPC_SYSLIB_PPC83XX_PCI_H
typedef struct immr_clk {
u32 spmr; /* system PLL mode Register */
u32 occr; /* output clock control Register */
u32 sccr; /* system clock control Register */
u8 res0[0xF4];
} immr_clk_t;
/*
* Sequencer
*/
typedef struct immr_ios {
u32 potar0;
u8 res0[4];
u32 pobar0;
u8 res1[4];
u32 pocmr0;
u8 res2[4];
u32 potar1;
u8 res3[4];
u32 pobar1;
u8 res4[4];
u32 pocmr1;
u8 res5[4];
u32 potar2;
u8 res6[4];
u32 pobar2;
u8 res7[4];
u32 pocmr2;
u8 res8[4];
u32 potar3;
u8 res9[4];
u32 pobar3;
u8 res10[4];
u32 pocmr3;
u8 res11[4];
u32 potar4;
u8 res12[4];
u32 pobar4;
u8 res13[4];
u32 pocmr4;
u8 res14[4];
u32 potar5;
u8 res15[4];
u32 pobar5;
u8 res16[4];
u32 pocmr5;
u8 res17[4];
u8 res18[0x60];
u32 pmcr;
u8 res19[4];
u32 dtcr;
u8 res20[4];
} immr_ios_t;
#define POTAR_TA_MASK 0x000fffff
#define POBAR_BA_MASK 0x000fffff
#define POCMR_EN 0x80000000
#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
#define POCMR_SE 0x20000000 /* streaming enable */
#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
#define POCMR_CM_MASK 0x000fffff
/*
* PCI Controller Control and Status Registers
*/
typedef struct immr_pcictrl {
u32 esr;
u32 ecdr;
u32 eer;
u32 eatcr;
u32 eacr;
u32 eeacr;
u32 edlcr;
u32 edhcr;
u32 gcr;
u32 ecr;
u32 gsr;
u8 res0[12];
u32 pitar2;
u8 res1[4];
u32 pibar2;
u32 piebar2;
u32 piwar2;
u8 res2[4];
u32 pitar1;
u8 res3[4];
u32 pibar1;
u32 piebar1;
u32 piwar1;
u8 res4[4];
u32 pitar0;
u8 res5[4];
u32 pibar0;
u8 res6[4];
u32 piwar0;
u8 res7[132];
} immr_pcictrl_t;
#define PITAR_TA_MASK 0x000fffff
#define PIBAR_MASK 0xffffffff
#define PIEBAR_EBA_MASK 0x000fffff
#define PIWAR_EN 0x80000000
#define PIWAR_PF 0x20000000
#define PIWAR_RTT_MASK 0x000f0000
#define PIWAR_RTT_NO_SNOOP 0x00040000
#define PIWAR_RTT_SNOOP 0x00050000
#define PIWAR_WTT_MASK 0x0000f000
#define PIWAR_WTT_NO_SNOOP 0x00004000
#define PIWAR_WTT_SNOOP 0x00005000
#define PIWAR_IWS_MASK 0x0000003F
#define PIWAR_IWS_4K 0x0000000B
#define PIWAR_IWS_8K 0x0000000C
#define PIWAR_IWS_16K 0x0000000D
#define PIWAR_IWS_32K 0x0000000E
#define PIWAR_IWS_64K 0x0000000F
#define PIWAR_IWS_128K 0x00000010
#define PIWAR_IWS_256K 0x00000011
#define PIWAR_IWS_512K 0x00000012
#define PIWAR_IWS_1M 0x00000013
#define PIWAR_IWS_2M 0x00000014
#define PIWAR_IWS_4M 0x00000015
#define PIWAR_IWS_8M 0x00000016
#define PIWAR_IWS_16M 0x00000017
#define PIWAR_IWS_32M 0x00000018
#define PIWAR_IWS_64M 0x00000019
#define PIWAR_IWS_128M 0x0000001A
#define PIWAR_IWS_256M 0x0000001B
#define PIWAR_IWS_512M 0x0000001C
#define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
arch/ppc/syslib/ppc83xx_setup.c deleted 100644 → 0
View file @ 80f4ec7f
This diff is collapsed.
arch/ppc/syslib/ppc83xx_setup.h deleted 100644 → 0
View file @ 80f4ec7f
/*
* MPC83XX common board definitions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H
#define __PPC_SYSLIB_PPC83XX_SETUP_H
#include <linux/init.h>
extern unsigned long mpc83xx_find_end_of_memory(void) __init;
extern long mpc83xx_time_init(void) __init;
extern void mpc83xx_calibrate_decr(void) __init;
extern void mpc83xx_early_serial_map(void) __init;
extern void mpc83xx_restart(char *cmd);
extern void mpc83xx_power_off(void);
extern void mpc83xx_halt(void);
extern void mpc83xx_setup_hose(void) __init;
/* PCI config */
#define PCI1_CFG_ADDR_OFFSET (0x8300)
#define PCI1_CFG_DATA_OFFSET (0x8304)
#define PCI2_CFG_ADDR_OFFSET (0x8380)
#define PCI2_CFG_DATA_OFFSET (0x8384)
/* Serial Config */
#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE 64
#else
#define RS_TABLE_SIZE 2
#endif
#ifndef BASE_BAUD
#define BASE_BAUD 115200
#endif
#endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */
include/asm-powerpc/irq.h
View file @ 3155f7f2
......@@ -483,11 +483,6 @@ static __inline__ int irq_canonicalize(int irq)
*/
#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#define NR_IRQS (NR_IPIC_INTS)
#elif defined(CONFIG_85xx)
/* Now include the board configuration specific associations.
*/
......
include/asm-ppc/mpc83xx.h deleted 100644 → 0
View file @ 80f4ec7f
/*
* include/asm-ppc/mpc83xx.h
*
* MPC83xx definitions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_MPC83xx_H__
#define __ASM_MPC83xx_H__
#include <asm/mmu.h>
#ifdef CONFIG_83xx
#ifdef CONFIG_MPC834x_SYS
#include <platforms/83xx/mpc834x_sys.h>
#endif
/*
* The "residual" board information structure the boot loader passes
* into the kernel.
*/
extern unsigned char __res[];
/* Internal IRQs on MPC83xx OpenPIC */
/* Not all of these exist on all MPC83xx implementations */
#ifndef MPC83xx_IPIC_IRQ_OFFSET
#define MPC83xx_IPIC_IRQ_OFFSET 0
#endif
#define NR_IPIC_INTS 128
#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
#define MPC83xx_CCSRBAR_SIZE (1024*1024)
/* Let modules/drivers get at immrbar (physical) */
extern phys_addr_t immrbar;
enum ppc_sys_devices {
MPC83xx_TSEC1,
MPC83xx_TSEC2,
MPC83xx_IIC1,
MPC83xx_IIC2,
MPC83xx_DUART,
MPC83xx_SEC2,
MPC83xx_USB2_DR,
MPC83xx_USB2_MPH,
MPC83xx_MDIO,
NUM_PPC_SYS_DEVS,
};
#endif /* CONFIG_83xx */
#endif /* __ASM_MPC83xx_H__ */
#endif /* __KERNEL__ */
include/asm-ppc/ppc_sys.h
View file @ 3155f7f2
......@@ -23,8 +23,6 @@
#if defined(CONFIG_8260)
#include <asm/mpc8260.h>
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
#elif defined(CONFIG_8xx)
......
include/asm-ppc/ppcboot.h
View file @ 3155f7f2
......@@ -38,8 +38,7 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\
defined(CONFIG_83xx)
#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_PPC_MPC52xx)
......@@ -74,7 +73,7 @@ typedef struct bd_info {
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \
defined(CONFIG_85xx) || defined(CONFIG_83xx)
defined(CONFIG_85xx)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
......
include/asm-ppc/serial.h
View file @ 3155f7f2
......@@ -29,8 +29,6 @@
#include <platforms/spruce.h>
#elif defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#elif defined(CONFIG_83xx)
#include <asm/mpc83xx.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
#elif defined(CONFIG_RADSTONE_PPC7D)
......
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