Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6

Documentation/block/biodoc.txt

@@ -1040,23 +1040,21 @@ Front merges are handled by the binary trees in AS and deadline schedulers.
 iii. Plugging the queue to batch requests in anticipation of opportunities for
      merge/sort optimizations
 
-This is just the same as in 2.4 so far, though per-device unplugging
-support is anticipated for 2.5. Also with a priority-based i/o scheduler,
-such decisions could be based on request priorities.
-
 Plugging is an approach that the current i/o scheduling algorithm resorts to so
 that it collects up enough requests in the queue to be able to take
 advantage of the sorting/merging logic in the elevator. If the
 queue is empty when a request comes in, then it plugs the request queue
-(sort of like plugging the bottom of a vessel to get fluid to build up)
+(sort of like plugging the bath tub of a vessel to get fluid to build up)
 till it fills up with a few more requests, before starting to service
 the requests. This provides an opportunity to merge/sort the requests before
 passing them down to the device. There are various conditions when the queue is
 unplugged (to open up the flow again), either through a scheduled task or
 could be on demand. For example wait_on_buffer sets the unplugging going
-(by running tq_disk) so the read gets satisfied soon. So in the read case,
-the queue gets explicitly unplugged as part of waiting for completion,
-in fact all queues get unplugged as a side-effect.
+through sync_buffer() running blk_run_address_space(mapping). Or the caller
+can do it explicity through blk_unplug(bdev). So in the read case,
+the queue gets explicitly unplugged as part of waiting for completion on that
+buffer. For page driven IO, the address space ->sync_page() takes care of
+doing the blk_run_address_space().
 
 Aside:
   This is kind of controversial territory, as it's not clear if plugging is
@@ -1067,11 +1065,6 @@ Aside:
   multi-page bios being queued in one shot, we may not need to wait to merge
   a big request from the broken up pieces coming by.
 
-  Per-queue granularity unplugging (still a Todo) may help reduce some of the
-  concerns with just a single tq_disk flush approach. Something like
-  blk_kick_queue() to unplug a specific queue (right away ?)
-  or optionally, all queues, is in the plan.
-
 4.4 I/O contexts
 I/O contexts provide a dynamically allocated per process data area. They may
 be used in I/O schedulers, and in the block layer (could be used for IO statis,

Documentation/powerpc/dts-bindings/fsl/i2c.txt

@@ -7,8 +7,10 @@ Required properties :
 
 Recommended properties :
 
- - compatible : Should be "fsl-i2c" for parts compatible with
-   Freescale I2C specifications.
+ - compatible : compatibility list with 2 entries, the first should
+   be "fsl,CHIP-i2c" where CHIP is the name of a compatible processor,
+   e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
+   should be "fsl-i2c".
  - interrupts : <a b> where a is the interrupt number and b is a
    field that represents an encoding of the sense and level
    information for the interrupt.  This should be encoded based on
@@ -16,17 +18,31 @@ Recommended properties :
    controller you have.
  - interrupt-parent : the phandle for the interrupt controller that
    services interrupts for this device.
- - dfsrr : boolean; if defined, indicates that this I2C device has
-   a digital filter sampling rate register
- - fsl5200-clocking : boolean; if defined, indicated that this device
-   uses the FSL 5200 clocking mechanism.
-
-Example :
-	i2c@3000 {
-		interrupt-parent = <40000>;
-		interrupts = <1b 3>;
-		reg = <3000 18>;
-		device_type = "i2c";
-		compatible  = "fsl-i2c";
-		dfsrr;
+ - fsl,preserve-clocking : boolean; if defined, the clock settings
+   from the bootloader are preserved (not touched).
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+
+Examples :
+
+	i2c@3d00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+		cell-index = <0>;
+		reg = <0x3d00 0x40>;
+		interrupts = <2 15 0>;
+		interrupt-parent = <&mpc5200_pic>;
+		fsl,preserve-clocking;
 	};
+
+	i2c@3100 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cell-index = <1>;
+		compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+		reg = <0x3100 0x100>;
+		interrupts = <43 2>;
+		interrupt-parent = <&mpic>;
+		clock-frequency = <400000>;
+	};
+

Documentation/sound/alsa/HD-Audio.txt

@@ -169,7 +169,7 @@ PCI SSID look-up.
 What `model` option values are available depends on the codec chip.
 Check your codec chip from the codec proc file (see "Codec Proc-File"
 section below).  It will show the vendor/product name of your codec
-chip.  Then, see Documentation/sound/alsa/HD-Audio-Modelstxt file,
+chip.  Then, see Documentation/sound/alsa/HD-Audio-Models.txt file,
 the section of HD-audio driver.  You can find a list of codecs
 and `model` options belonging to each codec.  For example, for Realtek
 ALC262 codec chip, pass `model=ultra` for devices that are compatible
@@ -177,7 +177,7 @@ with Samsung Q1 Ultra.
 
 Thus, the first thing you can do for any brand-new, unsupported and
 non-working HD-audio hardware is to check HD-audio codec and several
-different `model` option values.  If you have a luck, some of them
+different `model` option values.  If you have any luck, some of them
 might suit with your device well.
 
 Some codecs such as ALC880 have a special model option `model=test`.

arch/arm/mach-mx1/mx1ads.c

@@ -28,9 +28,7 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/irqs.h>
-#ifdef CONFIG_I2C_IMX
 #include <mach/i2c.h>
-#endif
 #include <mach/iomux.h>
 #include "devices.h"
 
@@ -114,7 +112,6 @@ static struct platform_device flash_device = {
  * I2C
  */
 
-#ifdef CONFIG_I2C_IMX
 static int i2c_pins[] = {
 	PA15_PF_I2C_SDA,
 	PA16_PF_I2C_SCL,
@@ -157,7 +154,6 @@ static struct i2c_board_info mx1ads_i2c_devices[] = {
 		.platform_data = &pcf857x_data[1],
 	},
 };
-#endif
 
 /*
  * Board init
@@ -172,12 +168,10 @@ static void __init mx1ads_init(void)
 	mxc_register_device(&flash_device, &mx1ads_flash_data);
 
 	/* I2C */
-#ifdef CONFIG_I2C_IMX
 	i2c_register_board_info(0, mx1ads_i2c_devices,
 				ARRAY_SIZE(mx1ads_i2c_devices));
 
 	mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
-#endif
 }
 
 static void __init mx1ads_timer_init(void)

arch/arm/mach-mx2/clock_imx21.c

@@ -919,19 +919,19 @@ static struct clk_lookup lookups[] __initdata = {
 	_REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
 	_REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
 	_REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
-	_REGISTER_CLOCK(NULL, "lcdc", lcdc_clk[0])
+	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
 	_REGISTER_CLOCK(NULL, "csi", csi_clk[0])
 	_REGISTER_CLOCK(NULL, "usb", usb_clk[0])
 	_REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
 	_REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
-	_REGISTER_CLOCK(NULL, "nfc", nfc_clk)
+	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 	_REGISTER_CLOCK(NULL, "dma", dma_clk[0])
 	_REGISTER_CLOCK(NULL, "brom", brom_clk)
 	_REGISTER_CLOCK(NULL, "emma", emma_clk[0])
 	_REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
-	_REGISTER_CLOCK(NULL, "wdog", wdog_clk)
+	_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
 	_REGISTER_CLOCK(NULL, "gpio", gpio_clk)
-	_REGISTER_CLOCK(NULL, "i2c", i2c_clk)
+	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
 	_REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
 	_REGISTER_CLOCK(NULL, "owire", owire_clk)
 	_REGISTER_CLOCK(NULL, "rtc", rtc_clk)

arch/arm/mach-mx3/Kconfig

@@ -19,6 +19,8 @@ config MACH_MX31ADS
 config MACH_MX31ADS_WM1133_EV1
 	bool "Support Wolfson Microelectronics 1133-EV1 module"
 	depends on MACH_MX31ADS
+	depends on MFD_WM8350_I2C
+	depends on REGULATOR_WM8350
 	select MFD_WM8350_CONFIG_MODE_0
 	select MFD_WM8352_CONFIG_MODE_0
 	help

arch/arm/mach-mx3/mx31ads.c

@@ -102,7 +102,7 @@ static struct imxuart_platform_data uart_pdata = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static int uart_pins[] = {
+static unsigned int uart_pins[] = {
 	MX31_PIN_CTS1__CTS1,
 	MX31_PIN_RTS1__RTS1,
 	MX31_PIN_TXD1__TXD1,
@@ -452,6 +452,8 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
 
 	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
 
+	regulator_has_full_constraints();
+
 	return 0;
 }
 

arch/arm/mach-mx3/pcm037.c

@@ -226,10 +226,10 @@ static void __init mxc_board_init(void)
 	mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire");
 	mxc_register_device(&mxc_w1_master_device, NULL);
 
-	/* SMSC9215 IRQ pin */
+	/* LAN9217 IRQ pin */
 	if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
 				"pcm037-eth"))
-		gpio_direction_input(MX31_PIN_GPIO3_1);
+		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
 
 #ifdef CONFIG_I2C_IMX
 	i2c_register_board_info(1, pcm037_i2c_devices,

arch/arm/mach-mx3/qong.c

@@ -250,32 +250,6 @@ static void __init qong_init_fpga(void)
 	qong_init_dnet();
 }
 
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc qong_io_desc[] __initdata = {
-	{
-		.virtual = AIPS1_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
-		.length = AIPS1_SIZE,
-		.type = MT_DEVICE_NONSHARED
-	}, {
-		.virtual = AIPS2_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
-		.length = AIPS2_SIZE,
-		.type = MT_DEVICE_NONSHARED
-	}
-};
-
-/*
- * Set up static virtual mappings.
- */
-static void __init qong_map_io(void)
-{
-	mxc_map_io();
-	iotable_init(qong_io_desc, ARRAY_SIZE(qong_io_desc));
-}
-
 /*
  * Board specific initialization.
  */
@@ -305,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
 	.phys_io        = AIPS1_BASE_ADDR,
 	.io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 	.boot_params    = PHYS_OFFSET + 0x100,
-	.map_io         = qong_map_io,
+	.map_io         = mxc_map_io,
 	.init_irq       = mxc_init_irq,
 	.init_machine   = mxc_board_init,
 	.timer          = &qong_timer,

arch/arm/plat-mxc/include/mach/imx-uart.h

@@ -27,6 +27,4 @@ struct imxuart_platform_data {
 	unsigned int flags;
 };
 
-int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
-
 #endif

arch/arm/plat-mxc/include/mach/irqs.h

@@ -45,7 +45,7 @@
 
 #define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)
 
-extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
+extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
 /* all normal IRQs can be FIQs */
 #define FIQ_START	0

arch/arm/plat-mxc/include/mach/mx21.h

@@ -54,9 +54,6 @@
 
 #define IRAM_BASE_ADDR          0xFFFFE800	/* internal ram */
 
-/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
-#define ARCH_NR_GPIOS		(6*32 + 16)
-
 /* fixed interrupt numbers */
 #define MXC_INT_USBCTRL         58
 #define MXC_INT_USBCTRL         58

arch/arm/plat-mxc/irq.c

@@ -50,23 +50,27 @@
 #define IIM_PROD_REV_SH		3
 #define IIM_PROD_REV_LEN	5
 
-#ifdef CONFIG_MXC_IRQ_PRIOR
-void imx_irq_set_priority(unsigned char irq, unsigned char prio)
+int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
+#ifdef CONFIG_MXC_IRQ_PRIOR
 	unsigned int temp;
 	unsigned int mask = 0x0F << irq % 8 * 4;
 
-	if (irq > 63)
-		return;
+	if (irq >= MXC_INTERNAL_IRQS)
+		return -EINVAL;;
 
 	temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
 	temp &= ~mask;
 	temp |= prio & mask;
 
 	__raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
+
+	return 0;
+#else
+	return -ENOSYS;
+#endif
 }
 EXPORT_SYMBOL(imx_irq_set_priority);
-#endif
 
 #ifdef CONFIG_FIQ
 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)