Commit 36d0f138 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'v4.13-next-dts64' of https://github.com/mbgg/linux-mediatek into next/dt64

Pull "arm: mediatek: dts64 updates for v4.14" from Matthias Brugger:

- add SoC mt7622 and its reference board
- cleanup of dts bindings
- mt6797: add watchdog and delete unused clock
- add support for SoC mt2701 and it's eval board

* tag 'v4.13-next-dts64' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: mediatek: Delete unused dummy clock for MT6797
  arm64: dts: mediatek: add watchdog to MT6797
  ARM: mediatek: dts: Add MT6797 binding
  ARM: mediatek: dts: Cleanup bindings documentation
  arm64: dts: mt7622: add dts file for MT7622 reference board variant 1
  arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
parents 395cd0e6 bdf2cbb2
...@@ -7,6 +7,7 @@ Required root node property: ...@@ -7,6 +7,7 @@ Required root node property:
compatible: Must contain one of compatible: Must contain one of
"mediatek,mt2701" "mediatek,mt2701"
"mediatek,mt2712"
"mediatek,mt6580" "mediatek,mt6580"
"mediatek,mt6589" "mediatek,mt6589"
"mediatek,mt6592" "mediatek,mt6592"
...@@ -25,6 +26,9 @@ Supported boards: ...@@ -25,6 +26,9 @@ Supported boards:
- Evaluation board for MT2701: - Evaluation board for MT2701:
Required root node properties: Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
- Evaluation board for MT2712:
Required root node properties:
- compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580: - Evaluation board for MT6580:
Required root node properties: Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
......
...@@ -17,6 +17,7 @@ Required properties: ...@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582 "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580 "mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577 "mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller - interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
......
...@@ -3,6 +3,7 @@ ...@@ -3,6 +3,7 @@
Required properties: Required properties:
- compatible should contain: - compatible should contain:
* "mediatek,mt2701-uart" for MT2701 compatible UARTS * "mediatek,mt2701-uart" for MT2701 compatible UARTS
* "mediatek,mt2712-uart" for MT2712 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS * "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS
......
...@@ -3,9 +3,9 @@ Mediatek SoCs Watchdog timer ...@@ -3,9 +3,9 @@ Mediatek SoCs Watchdog timer
Required properties: Required properties:
- compatible should contain: - compatible should contain:
* "mediatek,mt2701-wdt" for MT2701 compatible watchdog timers "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
* "mediatek,mt6589-wdt" for all compatible watchdog timers (MT2701, "mediatek,mt6589-wdt": for MT6589
MT6589) "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
......
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
always := $(dtb-y) always := $(dtb-y)
......
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: YT Shen <yt.shen@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include "mt2712e.dtsi"
/ {
model = "MediaTek MT2712 evaluation board";
compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: YT Shen <yt.shen@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt2712";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu2>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
baud_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
sys_clk: dummyclk {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
};
uart5: serial@1000f000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x1000f000 0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
sysirq: interrupt-controller@10220a80 {
compatible = "mediatek,mt2712-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220a80 0 0x40>;
};
gic: interrupt-controller@10510000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10510000 0 0x10000>,
<0 0x10520000 0 0x20000>,
<0 0x10540000 0 0x20000>,
<0 0x10560000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
reg = <0 0x11019000 0 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
};
...@@ -108,13 +108,6 @@ clk26m: oscillator@0 { ...@@ -108,13 +108,6 @@ clk26m: oscillator@0 {
clock-output-names = "clk26m"; clock-output-names = "clk26m";
}; };
clk32k: oscillator@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "clk32k";
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
...@@ -147,6 +140,11 @@ scpsys: scpsys@10006000 { ...@@ -147,6 +140,11 @@ scpsys: scpsys@10006000 {
infracfg = <&infrasys>; infracfg = <&infrasys>;
}; };
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
apmixedsys: apmixed@1000c000 { apmixedsys: apmixed@1000c000 {
compatible = "mediatek,mt6797-apmixedsys"; compatible = "mediatek,mt6797-apmixedsys";
reg = <0 0x1000c000 0 0x1000>; reg = <0 0x1000c000 0 0x1000>;
......
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ming Huang <ming.huang@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include "mt7622.dtsi"
/ {
model = "MediaTek MT7622 RFB1 board";
compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
chosen {
bootargs = "console=ttyS0,115200n1";
};
memory {
reg = <0 0x40000000 0 0x3F000000>;
};
};
&uart0 {
status = "okay";
};
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ming Huang <ming.huang@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt7622";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clock-frequency = <1300000000>;
};
};
uart_clk: dummy25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
bus_clk: dummy280m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <280000000>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
gic: interrupt-controller@10300000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10310000 0 0x1000>,
<0 0x10320000 0 0x1000>,
<0 0x10340000 0 0x2000>,
<0 0x10360000 0 0x2000>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>, <&bus_clk>;
clock-names = "baud", "bus";
status = "disabled";
};
};
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