drm/amd/display: add display write back(DWB)

Signed-off-by: Duke Du <Duke.Du@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -1749,6 +1749,16 @@ struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
 	return core_dc->links[link_index];
 }
 
+struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe)
+{
+	struct core_dc *core_dc = DC_TO_CORE(dc);
+	if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) {
+		return core_dc->res_pool->dwbc[(int)pipe];
+	} else {
+		return NULL;
+	}
+}
+
 const struct graphics_object_id dc_get_link_id_at_index(
 	struct dc *dc, uint32_t link_index)
 {

drivers/gpu/drm/amd/display/dc/dc.h

@@ -797,6 +797,8 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
  */
 struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);
 
+struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe);
+
 /* Return id of physical connector represented by a dc_link at link_index.*/
 const struct graphics_object_id dc_get_link_id_at_index(
 		struct dc *dc, uint32_t link_index);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

@@ -34,6 +34,7 @@
 
 #include "dce_clock_source.h"
 
+#include "core_dc.h"
 #include "reg_helper.h"
 
 #define REG(reg)\
@@ -602,6 +603,89 @@ static uint32_t dce110_get_pix_clk_dividers(
 	return pll_calc_error;
 }
 
+static uint32_t dce110_get_pll_pixel_rate_in_hz(
+	struct clock_source *cs,
+	struct pixel_clk_params *pix_clk_params,
+	struct pll_settings *pll_settings)
+{
+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+	struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);
+	struct validate_context *context = dc_core->current_context;
+	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
+
+	/* This function need separate to different DCE version, before separate, just use pixel clock */
+	return pipe_ctx->stream->phy_pix_clk;
+}
+
+static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
+	struct clock_source *cs,
+	struct pixel_clk_params *pix_clk_params,
+	struct pll_settings *pll_settings)
+{
+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+	struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);
+	struct validate_context *context = dc_core->current_context;
+	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
+
+	/* This function need separate to different DCE version, before separate, just use pixel clock */
+	return pipe_ctx->stream->phy_pix_clk;
+}
+
+static uint32_t dce110_get_d_to_pixel_rate_in_hz(
+	struct clock_source *cs,
+	struct pixel_clk_params *pix_clk_params,
+	struct pll_settings *pll_settings)
+{
+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
+	int dto_enabled = 0;
+	struct fixed31_32 pix_rate;
+
+	REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled);
+
+	if (dto_enabled) {
+		uint32_t phase = 0;
+		uint32_t modulo = 0;
+		REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase);
+		REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo);
+
+		if (modulo == 0) {
+			return 0;
+		}
+
+		pix_rate = dal_fixed31_32_from_int(clk_src->ref_freq_khz);
+		pix_rate = dal_fixed31_32_mul_int(pix_rate, 1000);
+		pix_rate = dal_fixed31_32_mul_int(pix_rate, phase);
+		pix_rate = dal_fixed31_32_div_int(pix_rate, modulo);
+
+		return dal_fixed31_32_round(pix_rate);
+	} else {
+		return dce110_get_dp_pixel_rate_from_combo_phy_pll(cs, pix_clk_params, pll_settings);
+	}
+}
+
+static uint32_t dce110_get_pix_rate_in_hz(
+	struct clock_source *cs,
+	struct pixel_clk_params *pix_clk_params,
+	struct pll_settings *pll_settings)
+{
+	uint32_t pix_rate = 0;
+	switch (pix_clk_params->signal_type) {
+	case	SIGNAL_TYPE_DISPLAY_PORT:
+	case	SIGNAL_TYPE_DISPLAY_PORT_MST:
+	case	SIGNAL_TYPE_EDP:
+	case	SIGNAL_TYPE_VIRTUAL:
+		pix_rate = dce110_get_d_to_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
+		break;
+	case	SIGNAL_TYPE_HDMI_TYPE_A:
+	default:
+		pix_rate = dce110_get_pll_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
+		break;
+	}
+
+	return pix_rate;
+}
+
 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
 {
 	enum bp_result result;
@@ -962,7 +1046,8 @@ static bool dce110_clock_source_power_down(
 static const struct clock_source_funcs dce110_clk_src_funcs = {
 	.cs_power_down = dce110_clock_source_power_down,
 	.program_pix_clk = dce110_program_pix_clk,
-	.get_pix_clk_dividers = dce110_get_pix_clk_dividers
+	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,
+	.get_pix_rate_in_hz = dce110_get_pix_rate_in_hz
 };
 
 static void get_ss_info_from_atombios(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

@@ -55,6 +55,8 @@
 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 		SRII(PHASE, DP_DTO, 0),\
@@ -71,9 +73,13 @@
 		SRII(PIXEL_RATE_CNTL, OTG, 3)
 
 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
+	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
+	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
 
+#endif
+
 #define CS_REG_FIELD_LIST(type) \
 	type PLL_REF_DIV_SRC; \
 	type DCCG_DEEP_COLOR_CNTL1; \
@@ -81,6 +87,8 @@
 	type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
 	type PLL_POST_DIV_PIXCLK; \
 	type PLL_REF_DIV; \
+	type DP_DTO0_PHASE; \
+	type DP_DTO0_MODULO; \
 	type DP_DTO0_ENABLE;
 
 struct dce110_clk_src_shift {

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

@@ -3,7 +3,7 @@
 
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
 		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
-		dcn10_mem_input.o dcn10_mpc.o
+		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_DWBC_DCN10_H__
+#define __DC_DWBC_DCN10_H__
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+
+bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
+#endif
+
+#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -32,6 +32,7 @@
 
 #include "dcn10/dcn10_ipp.h"
 #include "dcn10/dcn10_mpc.h"
+#include "dcn10/dcn10_dwb.h"
 #include "irq/dcn10/irq_service_dcn10.h"
 #include "dcn10/dcn10_dpp.h"
 #include "dcn10/dcn10_timing_generator.h"
@@ -410,6 +411,7 @@ static const struct resource_caps res_cap = {
 		.num_audio = 4,
 		.num_stream_encoder = 4,
 		.num_pll = 4,
+		.num_dwb = 2,
 };
 
 static const struct dc_debug debug_defaults_drv = {
@@ -1410,6 +1412,12 @@ static bool construct(
 		goto mpc_create_fail;
 	}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+	if (!dcn10_dwbc_create(ctx, &pool->base)) {
+		goto dwbc_create_fail;
+	}
+#endif
+
 	if (!resource_construct(num_virtual_links, dc, &pool->base,
 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
 			&res_create_funcs : &res_create_maximus_funcs)))
@@ -1432,6 +1440,7 @@ static bool construct(
 irqs_create_fail:
 res_create_fail:
 clock_source_create_fail:
+dwbc_create_fail:
 
 	destruct(pool);
 

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

@@ -166,6 +166,10 @@ struct clock_source_funcs {
 			struct clock_source *,
 			struct pixel_clk_params *,
 			struct pll_settings *);
+	uint32_t (*get_pix_rate_in_hz)(
+			struct clock_source *,
+			struct pixel_clk_params *,
+			struct pll_settings *);
 };
 
 struct clock_source {

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -32,7 +32,10 @@
 #include "ddc_service_types.h"
 #include "dc_bios_types.h"
 #include "mem_input.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 #include "mpc.h"
+#endif
+#include "dwb.h"
 
 #define MAX_CLOCK_SOURCES 7
 
@@ -125,6 +128,8 @@ struct resource_pool {
 	struct mpc *mpc;
 #endif
 
+	struct dwbc *dwbc[MAX_DWB_PIPES];
+
 	unsigned int pipe_count;
 	unsigned int underlay_pipe_index;
 	unsigned int stream_enc_count;
@@ -193,6 +198,7 @@ struct pipe_ctx {
 	struct _vcs_dpi_display_rq_regs_st rq_regs;
 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
 #endif
+	struct dwbc *dwbc;
 };
 
 struct resource_context {

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

+/* Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DWBC_H__
+#define __DC_DWBC_H__
+
+#include "dc_hw_types.h"
+
+#define MAX_DWB_PIPES	3
+
+enum dce_version;
+
+enum dwb_sw_version {
+	dwb_ver_1_0 = 1,
+};
+
+enum dwb_source {
+	dwb_src_scl = 0,	/* for DCE7x/9x, DCN won't support. */
+	dwb_src_blnd,		/* for DCE7x/9x */
+	dwb_src_fmt,		/* for DCE7x/9x */
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+	dwb_src_otg0 = 0x100,	/* for DCN1.x, register: mmDWB_SOURCE_SELECT */
+	dwb_src_otg1,		/* for DCN1.x */
+	dwb_src_otg2,		/* for DCN1.x */
+	dwb_src_otg3,		/* for DCN1.x */
+#endif
+};
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+/* DCN1.x supports 2 pipes */
+#endif
+enum dwb_pipe {
+	dwb_pipe0 = 0,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+	dwb_pipe1,
+#endif
+	dwb_pipe_max_num,
+};
+
+enum setting_flags {
+	sf_pipe				= 0x00000001,
+	sf_output_format	= 0x00000002,
+	sf_capture_rate		= 0x00000004,
+	sf_all				 = 0xffffffff,
+};
+
+enum dwb_capture_rate {
+
+	dwb_capture_rate_0 = 0,	/* Every frame is captured. */
+	dwb_capture_rate_1 = 1,	/* Every other frame is captured. */
+	dwb_capture_rate_2 = 2,	/* Every 3rd frame is captured. */
+	dwb_capture_rate_3 = 3,	/* Every 4th frame is captured. */
+};
+
+enum dwb_scaler_mode {
+	dwb_scaler_mode_bypass444 = 0,
+	dwb_scaler_mode_rgb444 = 1,
+	dwb_scaler_mode_yuv444 = 2,
+	dwb_scaler_mode_yuv420 = 3
+};
+
+struct dwb_caps {
+	enum dce_version hw_version;	/* DCN engine version. */
+	enum dwb_sw_version sw_version;	/* DWB sw implementation version. */
+	unsigned int	reserved[6];	/* Reserved for future use, MUST BE 0. */
+	unsigned int	adapter_id;
+	unsigned int	num_pipes;		/* number of DWB pipes */
+	struct {
+		unsigned int support_dwb					 :1;
+		unsigned int support_ogam					:1;
+		unsigned int support_wbscl					:1;
+		unsigned int support_ocsc					:1;
+	} caps;
+	unsigned int	 reserved2[10];	/* Reserved for future use, MUST BE 0. */
+};
+
+struct dwb_status {
+	bool			enabled;
+	/* Reserved ========================================================================= */
+	unsigned int	reserved[8];	/* Reserved fields */
+};
+
+struct dwb_basic_settings {
+	/* General DWB related input parameters ============================================= */
+	enum dwb_source	input_src_select;	 /* Select input source: (DCE) 0: SCL; 1: BLND; 2: FMT; (DCN) OTG* or MPC* */
+	enum dwb_pipe	input_pipe_select;	/* Select input pipe: 0: PIPE0; 1: PIPE1; 2: PIPE2 */
+
+	/* CNV: WND Related parameters ====================================================== */
+	unsigned int	capture_rate; /* Captures once every (capture_rate+1) frames */
+
+	/* CNV: CSC Related parameters ====================================================== */
+	unsigned int	start_x;	/* Horizontal window start position */
+	unsigned int	start_y;	/* Vertical window start position */
+	unsigned int	src_width;	/* Width of window captured within source window */
+	unsigned int	src_height;	/* Height of window captured within source window */
+
+	/* SISCL Related parameters ========================================================= */
+	unsigned int	dest_width; /* Destination width */
+	unsigned int	dest_height; /* Destination height */
+
+	/* MCIF bufer parameters	========================================================= */
+	unsigned long long luma_address[4];
+	unsigned long long chroma_address[4];
+	unsigned int	luma_pitch;
+	unsigned int	chroma_pitch;
+	unsigned int	slice_lines;
+
+	/* Reserved ========================================================================= */
+	unsigned int	reserved[8];	/* Reserved fields */
+
+};
+
+struct dwb_advanced_settings {
+	enum setting_flags		uFlag;
+	enum dwb_pipe			pipe;		/* default = DWB_PIPE_ALL */
+	enum dwb_scaler_mode	out_format;	/* default = DWBScalerMode_YUV420 */
+	enum dwb_capture_rate	capture_rate; /* default = Every frame is captured */
+	unsigned int			reserved[64]; /* reserved for future use, must be 0 */
+};
+
+/* / - dwb_frame_info is the info of the dumping data */
+struct dwb_frame_info {
+	unsigned int				 size;
+	unsigned int				 width;
+	unsigned int				 height;
+	unsigned int				 luma_pitch;
+	unsigned int				 chroma_pitch;
+	enum dwb_scaler_mode		 format;
+};
+
+struct dwbc_cfg {
+	struct	dwb_basic_settings basic_settings;
+	struct	dwb_advanced_settings advanced_settings;
+};
+
+struct dwbc {
+	const struct dwbc_funcs *funcs;
+	struct dc_context *ctx;
+	struct dwbc_cfg config;
+	struct dwb_status status;
+	int inst;
+};
+
+struct dwbc_funcs {
+	bool (*get_caps)(struct dwbc *dwbc, struct dwb_caps *caps);
+
+	bool (*enable)(struct dwbc *dwbc);
+
+	bool (*disable)(struct dwbc *dwbc);
+
+	bool (*get_status)(struct dwbc *dwbc, struct dwb_status *status);
+
+	bool (*dump_frame)(struct dwbc *dwbc, struct dwb_frame_info *frame_info,
+		unsigned char *luma_buffer, unsigned char *chroma_buffer,
+		unsigned char *dest_luma_buffer, unsigned char *dest_chroma_buffer);
+
+	bool (*set_basic_settings)(struct dwbc *dwbc,
+		const struct dwb_basic_settings *basic_settings);
+
+	bool (*get_basic_settings)(struct dwbc *dwbc,
+		struct dwb_basic_settings *basic_settings);
+
+	bool (*set_advanced_settings)(struct dwbc *dwbc,
+		const struct dwb_advanced_settings *advanced_settings);
+
+	bool (*get_advanced_settings)(struct dwbc *dwbc,
+		struct dwb_advanced_settings *advanced_settings);
+
+	bool (*reset_advanced_settings)(struct dwbc *dwbc);
+};
+
+#endif