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nexedi
linux
Commits
39bc30f2
Commit
39bc30f2
authored
Feb 19, 2017
by
Mark Brown
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Merge remote-tracking branches 'asoc/fix/fsl-mxs-saif' and 'asoc/fix/sunxi' into asoc-linus
parents
bd85d189
bcb8c270
ebad64d1
Changes
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2 changed files
with
29 additions
and
9 deletions
+29
-9
sound/soc/mxs/mxs-saif.c
sound/soc/mxs/mxs-saif.c
+27
-7
sound/soc/sunxi/sun4i-i2s.c
sound/soc/sunxi/sun4i-i2s.c
+2
-2
No files found.
sound/soc/mxs/mxs-saif.c
View file @
39bc30f2
...
...
@@ -119,23 +119,33 @@ static int mxs_saif_set_clk(struct mxs_saif *saif,
* Set SAIF clock
*
* The SAIF clock should be either 384*fs or 512*fs.
* If MCLK is used, the SAIF clk ratio need to match mclk ratio.
* For
32x mclk
, set saif clk as 512*fs.
* For
48x mclk
, set saif clk as 384*fs.
* If MCLK is used, the SAIF clk ratio need
s
to match mclk ratio.
* For
256x, 128x, 64x, and 32x sub-rates
, set saif clk as 512*fs.
* For
192x, 96x, and 48x sub-rates
, set saif clk as 384*fs.
*
* If MCLK is not used, we just set saif clk to 512*fs.
*/
clk_prepare_enable
(
master_saif
->
clk
);
if
(
master_saif
->
mclk_in_use
)
{
if
(
mclk
%
32
==
0
)
{
switch
(
mclk
/
rate
)
{
case
32
:
case
64
:
case
128
:
case
256
:
case
512
:
scr
&=
~
BM_SAIF_CTRL_BITCLK_BASE_RATE
;
ret
=
clk_set_rate
(
master_saif
->
clk
,
512
*
rate
);
}
else
if
(
mclk
%
48
==
0
)
{
break
;
case
48
:
case
96
:
case
192
:
case
384
:
scr
|=
BM_SAIF_CTRL_BITCLK_BASE_RATE
;
ret
=
clk_set_rate
(
master_saif
->
clk
,
384
*
rate
);
}
else
{
/* SAIF MCLK should be either 32x or 48x */
break
;
default:
/* SAIF MCLK should be a sub-rate of 512x or 384x */
clk_disable_unprepare
(
master_saif
->
clk
);
return
-
EINVAL
;
}
...
...
@@ -299,6 +309,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
return
-
EBUSY
;
}
/* If SAIF1 is configured as slave, the clk gate needs to be cleared
* before the register can be written.
*/
if
(
saif
->
id
!=
saif
->
master_id
)
{
__raw_writel
(
BM_SAIF_CTRL_SFTRST
,
saif
->
base
+
SAIF_CTRL
+
MXS_CLR_ADDR
);
__raw_writel
(
BM_SAIF_CTRL_CLKGATE
,
saif
->
base
+
SAIF_CTRL
+
MXS_CLR_ADDR
);
}
scr0
=
__raw_readl
(
saif
->
base
+
SAIF_CTRL
);
scr0
=
scr0
&
~
BM_SAIF_CTRL_BITCLK_EDGE
&
~
BM_SAIF_CTRL_LRCLK_POLARITY
\
&
~
BM_SAIF_CTRL_JUSTIFY
&
~
BM_SAIF_CTRL_DELAY
;
...
...
sound/soc/sunxi/sun4i-i2s.c
View file @
39bc30f2
...
...
@@ -694,10 +694,10 @@ static int sun4i_i2s_probe(struct platform_device *pdev)
}
i2s
->
playback_dma_data
.
addr
=
res
->
start
+
SUN4I_I2S_FIFO_TX_REG
;
i2s
->
playback_dma_data
.
maxburst
=
4
;
i2s
->
playback_dma_data
.
maxburst
=
8
;
i2s
->
capture_dma_data
.
addr
=
res
->
start
+
SUN4I_I2S_FIFO_RX_REG
;
i2s
->
capture_dma_data
.
maxburst
=
4
;
i2s
->
capture_dma_data
.
maxburst
=
8
;
pm_runtime_enable
(
&
pdev
->
dev
);
if
(
!
pm_runtime_enabled
(
&
pdev
->
dev
))
{
...
...
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