Commit 3d8b6e9c authored by Fabien Parent's avatar Fabien Parent Committed by Stephen Boyd

dt-bindings: mediatek: audsys: add support for MT8516

Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC.
Signed-off-by: default avatarFabien Parent <fparent@baylibre.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a188339c
...@@ -10,6 +10,7 @@ Required Properties: ...@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8183-audiosys", "syscon" - "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from The AUDSYS controller uses the common clk binding from
......
...@@ -208,4 +208,21 @@ ...@@ -208,4 +208,21 @@
#define CLK_TOP_MSDC2_INFRA 176 #define CLK_TOP_MSDC2_INFRA 176
#define CLK_TOP_NR_CLK 177 #define CLK_TOP_NR_CLK 177
/* AUDSYS */
#define CLK_AUD_AFE 0
#define CLK_AUD_I2S 1
#define CLK_AUD_22M 2
#define CLK_AUD_24M 3
#define CLK_AUD_INTDIR 4
#define CLK_AUD_APLL2_TUNER 5
#define CLK_AUD_APLL_TUNER 6
#define CLK_AUD_HDMI 7
#define CLK_AUD_SPDF 8
#define CLK_AUD_ADC 9
#define CLK_AUD_DAC 10
#define CLK_AUD_DAC_PREDIS 11
#define CLK_AUD_TML 12
#define CLK_AUD_NR_CLK 13
#endif /* _DT_BINDINGS_CLK_MT8516_H */ #endif /* _DT_BINDINGS_CLK_MT8516_H */
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