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Commit 3dc6475c authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller
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bcm63xx_enet: add support Broadcom BCM6345 Ethernet 

This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
has a slightly different and older DMA engine which requires the
following modifications:

- the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
  which means that the helpers enet_dma{c,s} need to account for this
  channel width and we can no longer use macros

- BCM6345 DMA engine does not have any internal SRAM for transfering
  buffers

- BCM6345 buffer allocation and flow control is not per-channel but
  global (done in RSET_ENETDMA)

- the DMA engine bits are right-shifted by 3 compared to other DMA
  generations

- the DMA enable/interrupt masks are a little different (we need to
  enabled more bits for 6345)

- some register have the same meaning but are offsetted in the ENET_DMAC
  space so a lookup table is required to return the proper offset

The MAC itself is identical and requires no modifications to work.
Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ca4ec90b
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 329 additions and 91 deletions
arch/mips/bcm63xx/dev-enet.c
View file @ 3dc6475c
......@@ -9,10 +9,44 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/export.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#ifdef BCMCPU_RUNTIME_DETECT
static const unsigned long bcm6348_regs_enetdmac[] = {
[ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
[ENETDMAC_IR] = ENETDMAC_IR_REG,
[ENETDMAC_IRMASK] = ENETDMAC_IRMASK_REG,
[ENETDMAC_MAXBURST] = ENETDMAC_MAXBURST_REG,
};
static const unsigned long bcm6345_regs_enetdmac[] = {
[ENETDMAC_CHANCFG] = ENETDMA_6345_CHANCFG_REG,
[ENETDMAC_IR] = ENETDMA_6345_IR_REG,
[ENETDMAC_IRMASK] = ENETDMA_6345_IRMASK_REG,
[ENETDMAC_MAXBURST] = ENETDMA_6345_MAXBURST_REG,
[ENETDMAC_BUFALLOC] = ENETDMA_6345_BUFALLOC_REG,
[ENETDMAC_RSTART] = ENETDMA_6345_RSTART_REG,
[ENETDMAC_FC] = ENETDMA_6345_FC_REG,
[ENETDMAC_LEN] = ENETDMA_6345_LEN_REG,
};
const unsigned long *bcm63xx_regs_enetdmac;
EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
static __init void bcm63xx_enetdmac_regs_init(void)
{
if (BCMCPU_IS_6345())
bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
else
bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac;
}
#else
static __init void bcm63xx_enetdmac_regs_init(void) { }
#endif
static struct resource shared_res[] = {
{
.start = -1, /* filled at runtime */
......@@ -137,12 +171,19 @@ static int __init register_shared(void)
if (shared_device_registered)
return 0;
bcm63xx_enetdmac_regs_init();
shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
shared_res[0].end = shared_res[0].start;
shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
if (BCMCPU_IS_6345())
shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
else
shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
chan_count = 32;
else if (BCMCPU_IS_6345())
chan_count = 8;
else
chan_count = 16;
......@@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int unit,
if (unit > 1)
return -ENODEV;
if (unit == 1 && BCMCPU_IS_6338())
if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
return -ENODEV;
ret = register_shared();
......@@ -213,6 +254,21 @@ int __init bcm63xx_enet_register(int unit,
dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
}
dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
if (BCMCPU_IS_6345()) {
dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
} else {
dpd->dma_has_sram = true;
dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
}
ret = platform_device_register(pdev);
if (ret)
return ret;
......@@ -246,6 +302,11 @@ bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd)
else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
enetsw_pd.num_ports = ENETSW_PORTS_6368;
enetsw_pd.dma_has_sram = true;
enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
ret = platform_device_register(&bcm63xx_enetsw_device);
if (ret)
return ret;
......
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
View file @ 3dc6475c
......@@ -174,6 +174,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_RSET_SPI_SIZE 1804
#define RSET_ENET_SIZE 2048
#define RSET_ENETDMA_SIZE 256
#define RSET_6345_ENETDMA_SIZE 64
#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
#define RSET_ENETSW_SIZE 65536
......@@ -300,7 +301,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800)
#define BCM_6345_ENETDMA_BASE (0xfffe2800)
#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
#define BCM_6345_ENETSW_BASE (0xdeadbeef)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
......
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
View file @ 3dc6475c
......@@ -4,6 +4,8 @@
#include <linux/if_ether.h>
#include <linux/init.h>
#include <bcm63xx_regs.h>
/*
* on board ethernet platform data
*/
......@@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
int phy_id, int reg),
void (*mii_write)(struct net_device *dev,
int phy_id, int reg, int val));
/* DMA channel enable mask */
u32 dma_chan_en_mask;
/* DMA channel interrupt mask */
u32 dma_chan_int_mask;
/* DMA engine has internal SRAM */
bool dma_has_sram;
/* DMA channel register width */
unsigned int dma_chan_width;
/* DMA descriptor shift */
unsigned int dma_desc_shift;
};
/*
......@@ -63,6 +80,18 @@ struct bcm63xx_enetsw_platform_data {
char mac_addr[ETH_ALEN];
int num_ports;
struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
/* DMA channel enable mask */
u32 dma_chan_en_mask;
/* DMA channel interrupt mask */
u32 dma_chan_int_mask;
/* DMA channel register width */
unsigned int dma_chan_width;
/* DMA engine has internal SRAM */
bool dma_has_sram;
};
int __init bcm63xx_enet_register(int unit,
......@@ -70,4 +99,69 @@ int __init bcm63xx_enet_register(int unit,
int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
enum bcm63xx_regs_enetdmac {
ENETDMAC_CHANCFG,
ENETDMAC_IR,
ENETDMAC_IRMASK,
ENETDMAC_MAXBURST,
ENETDMAC_BUFALLOC,
ENETDMAC_RSTART,
ENETDMAC_FC,
ENETDMAC_LEN,
};
static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
{
#ifdef BCMCPU_RUNTIME_DETECT
extern const unsigned long *bcm63xx_regs_enetdmac;
return bcm63xx_regs_enetdmac[reg];
#else
#ifdef CONFIG_BCM63XX_CPU_6345
switch (reg) {
case ENETDMAC_CHANCFG:
return ENETDMA_6345_CHANCFG_REG;
case ENETDMAC_IR:
return ENETDMA_6345_IR_REG;
case ENETDMAC_IRMASK:
return ENETDMA_6345_IRMASK_REG;
case ENETDMAC_MAXBURST:
return ENETDMA_6345_MAXBURST_REG;
case ENETDMAC_BUFALLOC:
return ENETDMA_6345_BUFALLOC_REG;
case ENETDMAC_RSTART:
return ENETDMA_6345_RSTART_REG;
case ENETDMAC_FC:
return ENETDMA_6345_FC_REG;
case ENETDMAC_LEN:
return ENETDMA_6345_LEN_REG;
}
#endif
#if defined(CONFIG_BCM63XX_CPU_6328) || \
defined(CONFIG_BCM63XX_CPU_6338) || \
defined(CONFIG_BCM63XX_CPU_6348) || \
defined(CONFIG_BCM63XX_CPU_6358) || \
defined(CONFIG_BCM63XX_CPU_6362) || \
defined(CONFIG_BCM63XX_CPU_6368)
switch (reg) {
case ENETDMAC_CHANCFG:
return ENETDMAC_CHANCFG_REG;
case ENETDMAC_IR:
return ENETDMAC_IR_REG;
case ENETDMAC_IRMASK:
return ENETDMAC_IRMASK_REG;
case ENETDMAC_MAXBURST:
return ENETDMAC_MAXBURST_REG;
case ENETDMAC_BUFALLOC:
case ENETDMAC_RSTART:
case ENETDMAC_FC:
case ENETDMAC_LEN:
return 0;
}
#endif
#endif
return 0;
}
#endif /* ! BCM63XX_DEV_ENET_H_ */
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
View file @ 3dc6475c
......@@ -727,6 +727,8 @@
/*************************************************************************
* _REG relative to RSET_ENETDMA
*************************************************************************/
#define ENETDMA_CHAN_WIDTH 0x10
#define ENETDMA_6345_CHAN_WIDTH 0x40
/* Controller Configuration Register */
#define ENETDMA_CFG_REG (0x0)
......@@ -782,31 +784,56 @@
/* State Ram Word 4 */
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
/* Broadcom 6345 ENET DMA definitions */
#define ENETDMA_6345_CHANCFG_REG (0x00)
#define ENETDMA_6345_MAXBURST_REG (0x40)
#define ENETDMA_6345_RSTART_REG (0x08)
#define ENETDMA_6345_LEN_REG (0x0C)
#define ENETDMA_6345_IR_REG (0x14)
#define ENETDMA_6345_IRMASK_REG (0x18)
#define ENETDMA_6345_FC_REG (0x1C)
#define ENETDMA_6345_BUFALLOC_REG (0x20)
/* Shift down for EOP, SOP and WRAP bits */
#define ENETDMA_6345_DESC_SHIFT (3)
/*************************************************************************
* _REG relative to RSET_ENETDMAC
*************************************************************************/
/* Channel Configuration register */
#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
#define ENETDMAC_CHANCFG_REG (0x0)
#define ENETDMAC_CHANCFG_EN_SHIFT 0
#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
/* Interrupt Control/Status register */
#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
#define ENETDMAC_IR_REG (0x4)
#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
/* Interrupt Mask register */
#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
#define ENETDMAC_IRMASK_REG (0x8)
/* Maximum Burst Length */
#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
#define ENETDMAC_MAXBURST_REG (0xc)
/*************************************************************************
......@@ -814,16 +841,16 @@
*************************************************************************/
/* Ring Start Address register */
#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
#define ENETDMAS_RSTART_REG (0x0)
/* State Ram Word 2 */
#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
#define ENETDMAS_SRAM2_REG (0x4)
/* State Ram Word 3 */
#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
#define ENETDMAS_SRAM3_REG (0x8)
/* State Ram Word 4 */
#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
#define ENETDMAS_SRAM4_REG (0xc)
/*************************************************************************
......
drivers/net/ethernet/broadcom/bcm63xx_enet.h
View file @ 3dc6475c
......@@ -339,6 +339,21 @@ struct bcm_enet_priv {
/* used to poll switch port state */
struct timer_list swphy_poll;
spinlock_t enetsw_mdio_lock;
/* dma channel enable mask */
u32 dma_chan_en_mask;
/* dma channel interrupt mask */
u32 dma_chan_int_mask;
/* DMA engine has internal SRAM */
bool dma_has_sram;
/* dma channel width */
unsigned int dma_chan_width;
/* dma descriptor shift value */
unsigned int dma_desc_shift;
};
......
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