Commit 453c5420 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter

drm/i915: panel power sequencing for VLV eDP v2

PPS register offsets have changed in Valleyview.

v2: don't clobber port select bits on VLV when fixing up PPS timings
    don't bother with G4x PPS regs (Jani)
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarGajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: default avatarVijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: default avatarBen Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b2634017
......@@ -4112,6 +4112,15 @@
#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
#define VLV_PIPE_PP_ON_DELAYS(pipe) \
_PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
_PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
#define VLV_PIPE_PP_DIVISOR(pipe) \
_PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
#define PANEL_UNLOCK_REGS (0xabcd << 16)
......
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