[ARM] Fix spacing in arch/arm/boot/Makefile and arch/arm/mm/Kconfig.

arch/arm/boot/Makefile

@@ -54,10 +54,8 @@ params_phys-$(CONFIG_ARCH_ADIFCC)	:= 0xc0000100
    zreladdr-$(CONFIG_ARCH_OMAP)		:= 0x10008000
 params_phys-$(CONFIG_ARCH_OMAP)		:= 0x10000100
 initrd_phys-$(CONFIG_ARCH_OMAP)		:= 0x10800000
-
-   zreladdr-$(CONFIG_ARCH_S3C2410)      := 0x30008000
-params_phys-$(CONFIG_ARCH_S3C2410)      := 0x30000100
-
+   zreladdr-$(CONFIG_ARCH_S3C2410)	:= 0x30008000
+params_phys-$(CONFIG_ARCH_S3C2410)	:= 0x30000100
 
 ZRELADDR    := $(zreladdr-y)
 ZTEXTADDR   := $(ztextaddr-y)

arch/arm/mm/Kconfig

@@ -355,7 +355,7 @@ config CPU_BIG_ENDIAN
 
 config CPU_ICACHE_DISABLE
 	bool "Disable I-Cache"
-	depends on CPU_ARM920T || CPU_ARM922T ||  CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
+	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020
 	help
 	  Say Y here to disable the processor instruction cache. Unless
 	  you have a reason not to or are unsure, say N.
@@ -369,7 +369,7 @@ config CPU_DCACHE_DISABLE
 
 config CPU_DCACHE_WRITETHROUGH
 	bool "Force write through D-cache"
-	depends on (CPU_ARM920T || CPU_ARM922T ||  CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
+	depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
 	help
 	  Say Y here to use the data cache in writethough mode. Unless you
 	  specifically require this or are unsure, say N.