MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3
In systems with CM3 & higher, the L2 cache is inclusive of the L1 dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true and we avoid some unnecessary cache ops during DMA cache maintenance. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14018/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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