drm/amd/include:cleanup raven1 nbio header files.

Cleanup asic_reg/raven1/NBIO folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

@@ -25,9 +25,9 @@
 #include "nbio_v7_0.h"
 
 #include "soc15ip.h"
-#include "raven1/NBIO/nbio_7_0_default.h"
-#include "raven1/NBIO/nbio_7_0_offset.h"
-#include "raven1/NBIO/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_offset.h"
+#include "nbio/nbio_7_0_sh_mask.h"
 #include "vega10_enum.h"
 
 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -55,7 +55,7 @@
 #include "dcn/dcn_1_0_offset.h"
 #include "dcn/dcn_1_0_sh_mask.h"
 
-#include "raven1/NBIO/nbio_7_0_offset.h"
+#include "nbio/nbio_7_0_offset.h"
 
 #include "mmhub/mmhub_9_1_offset.h"
 #include "mmhub/mmhub_9_1_sh_mask.h"

drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h

@@ -29,9 +29,9 @@
 #include "asic_reg/mp/mp_10_0_offset.h"
 #include "asic_reg/mp/mp_10_0_sh_mask.h"
 
-#include "asic_reg/raven1/NBIO/nbio_7_0_default.h"
-#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h"
-#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h"
+#include "asic_reg/nbio/nbio_7_0_default.h"
+#include "asic_reg/nbio/nbio_7_0_offset.h"
+#include "asic_reg/nbio/nbio_7_0_sh_mask.h"
 
 #include "asic_reg/raven1/THM/thm_10_0_default.h"
 #include "asic_reg/raven1/THM/thm_10_0_offset.h"