Commit 5c5b3b0e authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard

dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY

The Allwinner R40 HDMI PHY is currently the only one that seems to be
able to select between two PLL inputs.

Add a compatible string for it, and the pll-1 clock input definition.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180916043409.62374-3-icenowy@aosc.io
parent 69fdf420
...@@ -107,6 +107,7 @@ Required properties: ...@@ -107,6 +107,7 @@ Required properties:
- compatible: value must be one of: - compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy * allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy * allwinner,sun8i-h3-hdmi-phy
* allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy * allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region - reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY - clocks: phandles to the clocks feeding the HDMI PHY
...@@ -116,9 +117,9 @@ Required properties: ...@@ -116,9 +117,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY - resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy" - reset-names: must be "phy"
H3 and A64 HDMI PHY require additional clocks: H3, A64 and R40 HDMI PHY require additional clocks:
- pll-0: parent of phy clock - pll-0: parent of phy clock
- pll-1: second possible phy clock parent (A64 only) - pll-1: second possible phy clock parent (A64/R40 only)
TV Encoder TV Encoder
---------- ----------
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