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Commit 6256304b authored by Alan Cox's avatar Alan Cox Committed by Dave Airlie
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gma500: introduce a structure describing each pipe 

This starts the move away from lots of confused unions of per driver stuff
inherited when we merged the drivers together.
Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent a373bedd
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Showing with 173 additions and 340 deletions
drivers/gpu/drm/gma500/cdv_intel_display.c
View file @ 6256304b
...@@ -758,7 +758,7 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) ...@@ -758,7 +758,7 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev); gma_power_end(dev);
} else { } else {
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
dev_priv->regs.psb.save_palette_a[i] = dev_priv->regs.pipe[0].palette[i] =
((psb_intel_crtc->lut_r[i] + ((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) | psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] + ((psb_intel_crtc->lut_g[i] +
...@@ -1497,6 +1497,7 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev, ...@@ -1497,6 +1497,7 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
struct cdv_intel_clock_t clock; struct cdv_intel_clock_t clock;
bool is_lvds; bool is_lvds;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
...@@ -1507,18 +1508,11 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev, ...@@ -1507,18 +1508,11 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
dpll = (pipe == 0) ? dpll = p->dpll;
dev_priv->regs.psb.saveDPLL_A :
dev_priv->regs.psb.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ? fp = p->fp0;
dev_priv->regs.psb.saveFPA0 :
dev_priv->regs.psb.saveFPB0;
else else
fp = (pipe == 0) ? fp = p->fp1;
dev_priv->regs.psb.saveFPA1 :
dev_priv->regs.psb.saveFPB1;
is_lvds = (pipe == 1) && is_lvds = (pipe == 1) &&
(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
...@@ -1582,6 +1576,7 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, ...@@ -1582,6 +1576,7 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
int vtot; int vtot;
int vsync; int vsync;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
...@@ -1590,18 +1585,10 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, ...@@ -1590,18 +1585,10 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
htot = (pipe == 0) ? htot = p->htotal;
dev_priv->regs.psb.saveHTOTAL_A : hsync = p->hsync;
dev_priv->regs.psb.saveHTOTAL_B; vtot = p->vtotal;
hsync = (pipe == 0) ? vsync = p->vsync;
dev_priv->regs.psb.saveHSYNC_A :
dev_priv->regs.psb.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->regs.psb.saveVTOTAL_A :
dev_priv->regs.psb.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->regs.psb.saveVSYNC_A :
dev_priv->regs.psb.saveVSYNC_B;
} }
mode = kzalloc(sizeof(*mode), GFP_KERNEL); mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
drivers/gpu/drm/gma500/mdfld_device.c
View file @ 6256304b
...@@ -163,10 +163,11 @@ struct backlight_device *mdfld_get_backlight_device(void) ...@@ -163,10 +163,11 @@ struct backlight_device *mdfld_get_backlight_device(void)
* *
* Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
*/ */
static int mdfld_save_display_registers(struct drm_device *dev, int pipe) static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
{ {
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct medfield_state *regs = &dev_priv->regs.mdfld; struct medfield_state *regs = &dev_priv->regs.mdfld;
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
int i; int i;
/* register */ /* register */
...@@ -192,28 +193,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) ...@@ -192,28 +193,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
u32 palette_reg = PALETTE_A; u32 palette_reg = PALETTE_A;
/* pointer to values */ /* pointer to values */
u32 *dpll_val = &regs->saveDPLL_A; u32 *dpll_val = &pipe->dpll;
u32 *fp_val = &regs->saveFPA0; u32 *fp_val = &pipe->fp0;
u32 *pipeconf_val = &regs->savePIPEACONF; u32 *pipeconf_val = &pipe->conf;
u32 *htot_val = &regs->saveHTOTAL_A; u32 *htot_val = &pipe->htotal;
u32 *hblank_val = &regs->saveHBLANK_A; u32 *hblank_val = &pipe->hblank;
u32 *hsync_val = &regs->saveHSYNC_A; u32 *hsync_val = &pipe->hsync;
u32 *vtot_val = &regs->saveVTOTAL_A; u32 *vtot_val = &pipe->vtotal;
u32 *vblank_val = &regs->saveVBLANK_A; u32 *vblank_val = &pipe->vblank;
u32 *vsync_val = &regs->saveVSYNC_A; u32 *vsync_val = &pipe->vsync;
u32 *pipesrc_val = &regs->savePIPEASRC; u32 *pipesrc_val = &pipe->src;
u32 *dspstride_val = &regs->saveDSPASTRIDE; u32 *dspstride_val = &pipe->stride;
u32 *dsplinoff_val = &regs->saveDSPALINOFF; u32 *dsplinoff_val = &pipe->linoff;
u32 *dsptileoff_val = &regs->saveDSPATILEOFF; u32 *dsptileoff_val = &pipe->tileoff;
u32 *dspsize_val = &regs->saveDSPASIZE; u32 *dspsize_val = &pipe->size;
u32 *dsppos_val = &regs->saveDSPAPOS; u32 *dsppos_val = &pipe->pos;
u32 *dspsurf_val = &regs->saveDSPASURF; u32 *dspsurf_val = &pipe->surf;
u32 *mipi_val = &regs->saveMIPI; u32 *mipi_val = &regs->saveMIPI;
u32 *dspcntr_val = &regs->saveDSPACNTR; u32 *dspcntr_val = &pipe->cntr;
u32 *dspstatus_val = &regs->saveDSPASTATUS; u32 *dspstatus_val = &pipe->status;
u32 *palette_val = regs->save_palette_a; u32 *palette_val = pipe->palette;
switch (pipe) { switch (pipenum) {
case 0: case 0:
break; break;
case 1: case 1:
...@@ -237,27 +238,6 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) ...@@ -237,27 +238,6 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
dspcntr_reg = DSPBCNTR; dspcntr_reg = DSPBCNTR;
dspstatus_reg = PIPEBSTAT; dspstatus_reg = PIPEBSTAT;
palette_reg = PALETTE_B; palette_reg = PALETTE_B;
/* values */
dpll_val = &regs->saveDPLL_B;
fp_val = &regs->saveFPB0;
pipeconf_val = &regs->savePIPEBCONF;
htot_val = &regs->saveHTOTAL_B;
hblank_val = &regs->saveHBLANK_B;
hsync_val = &regs->saveHSYNC_B;
vtot_val = &regs->saveVTOTAL_B;
vblank_val = &regs->saveVBLANK_B;
vsync_val = &regs->saveVSYNC_B;
pipesrc_val = &regs->savePIPEBSRC;
dspstride_val = &regs->saveDSPBSTRIDE;
dsplinoff_val = &regs->saveDSPBLINOFF;
dsptileoff_val = &regs->saveDSPBTILEOFF;
dspsize_val = &regs->saveDSPBSIZE;
dsppos_val = &regs->saveDSPBPOS;
dspsurf_val = &regs->saveDSPBSURF;
dspcntr_val = &regs->saveDSPBCNTR;
dspstatus_val = &regs->saveDSPBSTATUS;
palette_val = regs->save_palette_b;
break; break;
case 2: case 2:
/* register */ /* register */
...@@ -281,24 +261,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) ...@@ -281,24 +261,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
palette_reg = PALETTE_C; palette_reg = PALETTE_C;
/* pointer to values */ /* pointer to values */
pipeconf_val = &regs->savePIPECCONF;
htot_val = &regs->saveHTOTAL_C;
hblank_val = &regs->saveHBLANK_C;
hsync_val = &regs->saveHSYNC_C;
vtot_val = &regs->saveVTOTAL_C;
vblank_val = &regs->saveVBLANK_C;
vsync_val = &regs->saveVSYNC_C;
pipesrc_val = &regs->savePIPECSRC;
dspstride_val = &regs->saveDSPCSTRIDE;
dsplinoff_val = &regs->saveDSPCLINOFF;
dsptileoff_val = &regs->saveDSPCTILEOFF;
dspsize_val = &regs->saveDSPCSIZE;
dsppos_val = &regs->saveDSPCPOS;
dspsurf_val = &regs->saveDSPCSURF;
mipi_val = &regs->saveMIPI_C; mipi_val = &regs->saveMIPI_C;
dspcntr_val = &regs->saveDSPCCNTR;
dspstatus_val = &regs->saveDSPCSTATUS;
palette_val = regs->save_palette_c;
break; break;
default: default:
DRM_ERROR("%s, invalid pipe number.\n", __func__); DRM_ERROR("%s, invalid pipe number.\n", __func__);
...@@ -329,7 +292,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) ...@@ -329,7 +292,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
palette_val[i] = PSB_RVDC32(palette_reg + (i << 2)); palette_val[i] = PSB_RVDC32(palette_reg + (i << 2));
if (pipe == 1) { if (pipenum == 1) {
regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
...@@ -349,7 +312,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe) ...@@ -349,7 +312,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
* *
* Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
*/ */
static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
{ {
/* To get panel out of ULPS mode. */ /* To get panel out of ULPS mode. */
u32 temp = 0; u32 temp = 0;
...@@ -357,11 +320,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -357,11 +320,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct mdfld_dsi_config *dsi_config = NULL; struct mdfld_dsi_config *dsi_config = NULL;
struct medfield_state *regs = &dev_priv->regs.mdfld; struct medfield_state *regs = &dev_priv->regs.mdfld;
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
u32 i = 0; u32 i = 0;
u32 dpll = 0; u32 dpll = 0;
u32 timeout = 0; u32 timeout = 0;
/* regester */ /* register */
u32 dpll_reg = MRST_DPLL_A; u32 dpll_reg = MRST_DPLL_A;
u32 fp_reg = MRST_FPA0; u32 fp_reg = MRST_FPA0;
u32 pipeconf_reg = PIPEACONF; u32 pipeconf_reg = PIPEACONF;
...@@ -384,33 +348,34 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -384,33 +348,34 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
u32 palette_reg = PALETTE_A; u32 palette_reg = PALETTE_A;
/* values */ /* values */
u32 dpll_val = regs->saveDPLL_A & ~DPLL_VCO_ENABLE; u32 dpll_val = pipe->dpll;
u32 fp_val = regs->saveFPA0; u32 fp_val = pipe->fp0;
u32 pipeconf_val = regs->savePIPEACONF; u32 pipeconf_val = pipe->conf;
u32 htot_val = regs->saveHTOTAL_A; u32 htot_val = pipe->htotal;
u32 hblank_val = regs->saveHBLANK_A; u32 hblank_val = pipe->hblank;
u32 hsync_val = regs->saveHSYNC_A; u32 hsync_val = pipe->hsync;
u32 vtot_val = regs->saveVTOTAL_A; u32 vtot_val = pipe->vtotal;
u32 vblank_val = regs->saveVBLANK_A; u32 vblank_val = pipe->vblank;
u32 vsync_val = regs->saveVSYNC_A; u32 vsync_val = pipe->vsync;
u32 pipesrc_val = regs->savePIPEASRC; u32 pipesrc_val = pipe->src;
u32 dspstride_val = regs->saveDSPASTRIDE; u32 dspstride_val = pipe->stride;
u32 dsplinoff_val = regs->saveDSPALINOFF; u32 dsplinoff_val = pipe->linoff;
u32 dsptileoff_val = regs->saveDSPATILEOFF; u32 dsptileoff_val = pipe->tileoff;
u32 dspsize_val = regs->saveDSPASIZE; u32 dspsize_val = pipe->size;
u32 dsppos_val = regs->saveDSPAPOS; u32 dsppos_val = pipe->pos;
u32 dspsurf_val = regs->saveDSPASURF; u32 dspsurf_val = pipe->surf;
u32 dspstatus_val = regs->saveDSPASTATUS; u32 dspstatus_val = pipe->status;
u32 mipi_val = regs->saveMIPI; u32 mipi_val = regs->saveMIPI;
u32 dspcntr_val = regs->saveDSPACNTR; u32 dspcntr_val = pipe->cntr;
u32 *palette_val = regs->save_palette_a; u32 *palette_val = pipe->palette;
switch (pipe) { switch (pipenum) {
case 0: case 0:
dpll_val &= ~DPLL_VCO_ENABLE;
dsi_config = dev_priv->dsi_configs[0]; dsi_config = dev_priv->dsi_configs[0];
break; break;
case 1: case 1:
/* regester */ /* register */
dpll_reg = MDFLD_DPLL_B; dpll_reg = MDFLD_DPLL_B;
fp_reg = MDFLD_DPLL_DIV0; fp_reg = MDFLD_DPLL_DIV0;
pipeconf_reg = PIPEBCONF; pipeconf_reg = PIPEBCONF;
...@@ -432,28 +397,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -432,28 +397,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
palette_reg = PALETTE_B; palette_reg = PALETTE_B;
/* values */ /* values */
dpll_val = regs->saveDPLL_B & ~DPLL_VCO_ENABLE; dpll_val &= ~DPLL_VCO_ENABLE;
fp_val = regs->saveFPB0;
pipeconf_val = regs->savePIPEBCONF;
htot_val = regs->saveHTOTAL_B;
hblank_val = regs->saveHBLANK_B;
hsync_val = regs->saveHSYNC_B;
vtot_val = regs->saveVTOTAL_B;
vblank_val = regs->saveVBLANK_B;
vsync_val = regs->saveVSYNC_B;
pipesrc_val = regs->savePIPEBSRC;
dspstride_val = regs->saveDSPBSTRIDE;
dsplinoff_val = regs->saveDSPBLINOFF;
dsptileoff_val = regs->saveDSPBTILEOFF;
dspsize_val = regs->saveDSPBSIZE;
dsppos_val = regs->saveDSPBPOS;
dspsurf_val = regs->saveDSPBSURF;
dspcntr_val = regs->saveDSPBCNTR;
dspstatus_val = regs->saveDSPBSTATUS;
palette_val = regs->save_palette_b;
break; break;
case 2: case 2:
/* regester */ /* register */
pipeconf_reg = PIPECCONF; pipeconf_reg = PIPECCONF;
htot_reg = HTOTAL_C; htot_reg = HTOTAL_C;
hblank_reg = HBLANK_C; hblank_reg = HBLANK_C;
...@@ -474,25 +421,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -474,25 +421,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
palette_reg = PALETTE_C; palette_reg = PALETTE_C;
/* values */ /* values */
pipeconf_val = regs->savePIPECCONF;
htot_val = regs->saveHTOTAL_C;
hblank_val = regs->saveHBLANK_C;
hsync_val = regs->saveHSYNC_C;
vtot_val = regs->saveVTOTAL_C;
vblank_val = regs->saveVBLANK_C;
vsync_val = regs->saveVSYNC_C;
pipesrc_val = regs->savePIPECSRC;
dspstride_val = regs->saveDSPCSTRIDE;
dsplinoff_val = regs->saveDSPCLINOFF;
dsptileoff_val = regs->saveDSPCTILEOFF;
dspsize_val = regs->saveDSPCSIZE;
dsppos_val = regs->saveDSPCPOS;
dspsurf_val = regs->saveDSPCSURF;
mipi_val = regs->saveMIPI_C; mipi_val = regs->saveMIPI_C;
dspcntr_val = regs->saveDSPCCNTR;
dspstatus_val = regs->saveDSPCSTATUS;
palette_val = regs->save_palette_c;
dsi_config = dev_priv->dsi_configs[1]; dsi_config = dev_priv->dsi_configs[1];
break; break;
default: default:
...@@ -503,7 +432,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -503,7 +432,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
/*make sure VGA plane is off. it initializes to on after reset!*/ /*make sure VGA plane is off. it initializes to on after reset!*/
PSB_WVDC32(0x80000000, VGACNTRL); PSB_WVDC32(0x80000000, VGACNTRL);
if (pipe == 1) { if (pipenum == 1) {
PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg); PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg);
PSB_RVDC32(dpll_reg); PSB_RVDC32(dpll_reg);
...@@ -564,7 +493,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -564,7 +493,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
PSB_WVDC32(dsppos_val, dsppos_reg); PSB_WVDC32(dsppos_val, dsppos_reg);
PSB_WVDC32(dspsurf_val, dspsurf_reg); PSB_WVDC32(dspsurf_val, dspsurf_reg);
if (pipe == 1) { if (pipenum == 1) {
/* restore palette (gamma) */ /* restore palette (gamma) */
/*DRM_UDELAY(50000); */ /*DRM_UDELAY(50000); */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
...@@ -588,7 +517,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) ...@@ -588,7 +517,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
/*setup MIPI adapter + MIPI IP registers*/ /*setup MIPI adapter + MIPI IP registers*/
if (dsi_config) if (dsi_config)
mdfld_dsi_controller_init(dsi_config, pipe); mdfld_dsi_controller_init(dsi_config, pipenum);
if (in_atomic() || in_interrupt()) if (in_atomic() || in_interrupt())
mdelay(20); mdelay(20);
......
drivers/gpu/drm/gma500/oaktrail_device.c
View file @ 6256304b
...@@ -187,6 +187,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev) ...@@ -187,6 +187,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
{ {
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_save_area *regs = &dev_priv->regs; struct psb_save_area *regs = &dev_priv->regs;
struct psb_pipe *p = &regs->pipe[0];
int i; int i;
u32 pp_stat; u32 pp_stat;
...@@ -201,24 +202,24 @@ static int oaktrail_save_display_registers(struct drm_device *dev) ...@@ -201,24 +202,24 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
/* Pipe & plane A info */ /* Pipe & plane A info */
regs->psb.savePIPEACONF = PSB_RVDC32(PIPEACONF); p->conf = PSB_RVDC32(PIPEACONF);
regs->psb.savePIPEASRC = PSB_RVDC32(PIPEASRC); p->src = PSB_RVDC32(PIPEASRC);
regs->psb.saveFPA0 = PSB_RVDC32(MRST_FPA0); p->fp0 = PSB_RVDC32(MRST_FPA0);
regs->psb.saveFPA1 = PSB_RVDC32(MRST_FPA1); p->fp1 = PSB_RVDC32(MRST_FPA1);
regs->psb.saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); p->dpll = PSB_RVDC32(MRST_DPLL_A);
regs->psb.saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); p->htotal = PSB_RVDC32(HTOTAL_A);
regs->psb.saveHBLANK_A = PSB_RVDC32(HBLANK_A); p->hblank = PSB_RVDC32(HBLANK_A);
regs->psb.saveHSYNC_A = PSB_RVDC32(HSYNC_A); p->hsync = PSB_RVDC32(HSYNC_A);
regs->psb.saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); p->vtotal = PSB_RVDC32(VTOTAL_A);
regs->psb.saveVBLANK_A = PSB_RVDC32(VBLANK_A); p->vblank = PSB_RVDC32(VBLANK_A);
regs->psb.saveVSYNC_A = PSB_RVDC32(VSYNC_A); p->vsync = PSB_RVDC32(VSYNC_A);
regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
regs->psb.saveDSPACNTR = PSB_RVDC32(DSPACNTR); p->cntr = PSB_RVDC32(DSPACNTR);
regs->psb.saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); p->stride = PSB_RVDC32(DSPASTRIDE);
regs->psb.saveDSPAADDR = PSB_RVDC32(DSPABASE); p->addr = PSB_RVDC32(DSPABASE);
regs->psb.saveDSPASURF = PSB_RVDC32(DSPASURF); p->surf = PSB_RVDC32(DSPASURF);
regs->psb.saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); p->linoff = PSB_RVDC32(DSPALINOFF);
regs->psb.saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); p->tileoff = PSB_RVDC32(DSPATILEOFF);
/* Save cursor regs */ /* Save cursor regs */
regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
...@@ -227,7 +228,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev) ...@@ -227,7 +228,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
/* Save palette (gamma) */ /* Save palette (gamma) */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
regs->psb.save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
if (dev_priv->hdmi_priv) if (dev_priv->hdmi_priv)
oaktrail_hdmi_save(dev); oaktrail_hdmi_save(dev);
...@@ -300,6 +301,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev) ...@@ -300,6 +301,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
{ {
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_save_area *regs = &dev_priv->regs; struct psb_save_area *regs = &dev_priv->regs;
struct psb_pipe *p = &regs->pipe[0];
u32 pp_stat; u32 pp_stat;
int i; int i;
...@@ -317,21 +319,21 @@ static int oaktrail_restore_display_registers(struct drm_device *dev) ...@@ -317,21 +319,21 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
PSB_WVDC32(0x80000000, VGACNTRL); PSB_WVDC32(0x80000000, VGACNTRL);
/* set the plls */ /* set the plls */
PSB_WVDC32(regs->psb.saveFPA0, MRST_FPA0); PSB_WVDC32(p->fp0, MRST_FPA0);
PSB_WVDC32(regs->psb.saveFPA1, MRST_FPA1); PSB_WVDC32(p->fp1, MRST_FPA1);
/* Actually enable it */ /* Actually enable it */
PSB_WVDC32(regs->psb.saveDPLL_A, MRST_DPLL_A); PSB_WVDC32(p->dpll, MRST_DPLL_A);
DRM_UDELAY(150); DRM_UDELAY(150);
/* Restore mode */ /* Restore mode */
PSB_WVDC32(regs->psb.saveHTOTAL_A, HTOTAL_A); PSB_WVDC32(p->htotal, HTOTAL_A);
PSB_WVDC32(regs->psb.saveHBLANK_A, HBLANK_A); PSB_WVDC32(p->hblank, HBLANK_A);
PSB_WVDC32(regs->psb.saveHSYNC_A, HSYNC_A); PSB_WVDC32(p->hsync, HSYNC_A);
PSB_WVDC32(regs->psb.saveVTOTAL_A, VTOTAL_A); PSB_WVDC32(p->vtotal, VTOTAL_A);
PSB_WVDC32(regs->psb.saveVBLANK_A, VBLANK_A); PSB_WVDC32(p->vblank, VBLANK_A);
PSB_WVDC32(regs->psb.saveVSYNC_A, VSYNC_A); PSB_WVDC32(p->vsync, VSYNC_A);
PSB_WVDC32(regs->psb.savePIPEASRC, PIPEASRC); PSB_WVDC32(p->src, PIPEASRC);
PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
/* Restore performance mode*/ /* Restore performance mode*/
...@@ -339,16 +341,16 @@ static int oaktrail_restore_display_registers(struct drm_device *dev) ...@@ -339,16 +341,16 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
/* Enable the pipe*/ /* Enable the pipe*/
if (dev_priv->iLVDS_enable) if (dev_priv->iLVDS_enable)
PSB_WVDC32(regs->psb.savePIPEACONF, PIPEACONF); PSB_WVDC32(p->conf, PIPEACONF);
/* Set up the plane*/ /* Set up the plane*/
PSB_WVDC32(regs->psb.saveDSPALINOFF, DSPALINOFF); PSB_WVDC32(p->linoff, DSPALINOFF);
PSB_WVDC32(regs->psb.saveDSPASTRIDE, DSPASTRIDE); PSB_WVDC32(p->stride, DSPASTRIDE);
PSB_WVDC32(regs->psb.saveDSPATILEOFF, DSPATILEOFF); PSB_WVDC32(p->tileoff, DSPATILEOFF);
/* Enable the plane */ /* Enable the plane */
PSB_WVDC32(regs->psb.saveDSPACNTR, DSPACNTR); PSB_WVDC32(p->cntr, DSPACNTR);
PSB_WVDC32(regs->psb.saveDSPASURF, DSPASURF); PSB_WVDC32(p->surf, DSPASURF);
/* Enable Cursor A */ /* Enable Cursor A */
PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
...@@ -357,7 +359,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev) ...@@ -357,7 +359,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
/* Restore palette (gamma) */ /* Restore palette (gamma) */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
PSB_WVDC32(regs->psb.save_palette_a[i], PALETTE_A + (i << 2)); PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
if (dev_priv->hdmi_priv) if (dev_priv->hdmi_priv)
oaktrail_hdmi_restore(dev); oaktrail_hdmi_restore(dev);
......
drivers/gpu/drm/gma500/oaktrail_hdmi.c
View file @ 6256304b
...@@ -434,6 +434,7 @@ void oaktrail_hdmi_save(struct drm_device *dev) ...@@ -434,6 +434,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs.psb; struct psb_state *regs = &dev_priv->regs.psb;
struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
int i; int i;
/* dpll */ /* dpll */
...@@ -444,14 +445,14 @@ void oaktrail_hdmi_save(struct drm_device *dev) ...@@ -444,14 +445,14 @@ void oaktrail_hdmi_save(struct drm_device *dev)
hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
/* pipe B */ /* pipe B */
regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF); pipeb->conf = PSB_RVDC32(PIPEBCONF);
regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC); pipeb->src = PSB_RVDC32(PIPEBSRC);
regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B); pipeb->htotal = PSB_RVDC32(HTOTAL_B);
regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B); pipeb->hblank = PSB_RVDC32(HBLANK_B);
regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B); pipeb->hsync = PSB_RVDC32(HSYNC_B);
regs->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B); pipeb->vtotal = PSB_RVDC32(VTOTAL_B);
regs->saveVBLANK_B = PSB_RVDC32(VBLANK_B); pipeb->vblank = PSB_RVDC32(VBLANK_B);
regs->saveVSYNC_B = PSB_RVDC32(VSYNC_B); pipeb->vsync = PSB_RVDC32(VSYNC_B);
hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
...@@ -463,12 +464,12 @@ void oaktrail_hdmi_save(struct drm_device *dev) ...@@ -463,12 +464,12 @@ void oaktrail_hdmi_save(struct drm_device *dev)
hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
/* plane */ /* plane */
regs->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR); pipeb->cntr = PSB_RVDC32(DSPBCNTR);
regs->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE); pipeb->stride = PSB_RVDC32(DSPBSTRIDE);
regs->saveDSPBADDR = PSB_RVDC32(DSPBBASE); pipeb->addr = PSB_RVDC32(DSPBBASE);
regs->saveDSPBSURF = PSB_RVDC32(DSPBSURF); pipeb->surf = PSB_RVDC32(DSPBSURF);
regs->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF); pipeb->linoff = PSB_RVDC32(DSPBLINOFF);
regs->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF); pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF);
/* cursor B */ /* cursor B */
regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
...@@ -477,7 +478,7 @@ void oaktrail_hdmi_save(struct drm_device *dev) ...@@ -477,7 +478,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
/* save palette */ /* save palette */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
regs->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2)); pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2));
} }
/* restore HDMI register state */ /* restore HDMI register state */
...@@ -486,6 +487,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev) ...@@ -486,6 +487,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
struct psb_state *regs = &dev_priv->regs.psb; struct psb_state *regs = &dev_priv->regs.psb;
struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
int i; int i;
/* dpll */ /* dpll */
...@@ -497,13 +499,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev) ...@@ -497,13 +499,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
DRM_UDELAY(150); DRM_UDELAY(150);
/* pipe */ /* pipe */
PSB_WVDC32(regs->savePIPEBSRC, PIPEBSRC); PSB_WVDC32(pipeb->src, PIPEBSRC);
PSB_WVDC32(regs->saveHTOTAL_B, HTOTAL_B); PSB_WVDC32(pipeb->htotal, HTOTAL_B);
PSB_WVDC32(regs->saveHBLANK_B, HBLANK_B); PSB_WVDC32(pipeb->hblank, HBLANK_B);
PSB_WVDC32(regs->saveHSYNC_B, HSYNC_B); PSB_WVDC32(pipeb->hsync, HSYNC_B);
PSB_WVDC32(regs->saveVTOTAL_B, VTOTAL_B); PSB_WVDC32(pipeb->vtotal, VTOTAL_B);
PSB_WVDC32(regs->saveVBLANK_B, VBLANK_B); PSB_WVDC32(pipeb->vblank, VBLANK_B);
PSB_WVDC32(regs->saveVSYNC_B, VSYNC_B); PSB_WVDC32(pipeb->vsync, VSYNC_B);
PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
...@@ -513,15 +515,15 @@ void oaktrail_hdmi_restore(struct drm_device *dev) ...@@ -513,15 +515,15 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
PSB_WVDC32(regs->savePIPEBCONF, PIPEBCONF); PSB_WVDC32(pipeb->conf, PIPEBCONF);
PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
/* plane */ /* plane */
PSB_WVDC32(regs->saveDSPBLINOFF, DSPBLINOFF); PSB_WVDC32(pipeb->linoff, DSPBLINOFF);
PSB_WVDC32(regs->saveDSPBSTRIDE, DSPBSTRIDE); PSB_WVDC32(pipeb->stride, DSPBSTRIDE);
PSB_WVDC32(regs->saveDSPBTILEOFF, DSPBTILEOFF); PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF);
PSB_WVDC32(regs->saveDSPBCNTR, DSPBCNTR); PSB_WVDC32(pipeb->cntr, DSPBCNTR);
PSB_WVDC32(regs->saveDSPBSURF, DSPBSURF); PSB_WVDC32(pipeb->surf, DSPBSURF);
/* cursor B */ /* cursor B */
PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR); PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
...@@ -530,5 +532,5 @@ void oaktrail_hdmi_restore(struct drm_device *dev) ...@@ -530,5 +532,5 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
/* restore palette */ /* restore palette */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2)); PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2));
} }
drivers/gpu/drm/gma500/psb_drv.h
View file @ 6256304b
...@@ -286,45 +286,37 @@ struct intel_gmbus { ...@@ -286,45 +286,37 @@ struct intel_gmbus {
* yet) include screen blank. Operations occuring during the save * yet) include screen blank. Operations occuring during the save
* update the register cache instead. * update the register cache instead.
*/ */
/*
* Common status for pipes.
*/
struct psb_pipe {
u32 fp0;
u32 fp1;
u32 cntr;
u32 conf;
u32 src;
u32 dpll;
u32 dpll_md;
u32 htotal;
u32 hblank;
u32 hsync;
u32 vtotal;
u32 vblank;
u32 vsync;
u32 stride;
u32 size;
u32 pos;
u32 base;
u32 surf;
u32 addr;
u32 status;
u32 linoff;
u32 tileoff;
u32 palette[256];
};
struct psb_state { struct psb_state {
uint32_t saveDSPACNTR;
uint32_t saveDSPBCNTR;
uint32_t savePIPEACONF;
uint32_t savePIPEBCONF;
uint32_t savePIPEASRC;
uint32_t savePIPEBSRC;
uint32_t saveFPA0;
uint32_t saveFPA1;
uint32_t saveDPLL_A;
uint32_t saveDPLL_A_MD;
uint32_t saveHTOTAL_A;
uint32_t saveHBLANK_A;
uint32_t saveHSYNC_A;
uint32_t saveVTOTAL_A;
uint32_t saveVBLANK_A;
uint32_t saveVSYNC_A;
uint32_t saveDSPASTRIDE;
uint32_t saveDSPASIZE;
uint32_t saveDSPAPOS;
uint32_t saveDSPABASE;
uint32_t saveDSPASURF;
uint32_t saveDSPASTATUS;
uint32_t saveFPB0;
uint32_t saveFPB1;
uint32_t saveDPLL_B;
uint32_t saveDPLL_B_MD;
uint32_t saveHTOTAL_B;
uint32_t saveHBLANK_B;
uint32_t saveHSYNC_B;
uint32_t saveVTOTAL_B;
uint32_t saveVBLANK_B;
uint32_t saveVSYNC_B;
uint32_t saveDSPBSTRIDE;
uint32_t saveDSPBSIZE;
uint32_t saveDSPBPOS;
uint32_t saveDSPBBASE;
uint32_t saveDSPBSURF;
uint32_t saveDSPBSTATUS;
uint32_t saveVCLK_DIVISOR_VGA0; uint32_t saveVCLK_DIVISOR_VGA0;
uint32_t saveVCLK_DIVISOR_VGA1; uint32_t saveVCLK_DIVISOR_VGA1;
uint32_t saveVCLK_POST_DIV; uint32_t saveVCLK_POST_DIV;
...@@ -339,14 +331,8 @@ struct psb_state { ...@@ -339,14 +331,8 @@ struct psb_state {
uint32_t savePP_CONTROL; uint32_t savePP_CONTROL;
uint32_t savePP_CYCLE; uint32_t savePP_CYCLE;
uint32_t savePFIT_CONTROL; uint32_t savePFIT_CONTROL;
uint32_t savePaletteA[256];
uint32_t savePaletteB[256];
uint32_t saveCLOCKGATING; uint32_t saveCLOCKGATING;
uint32_t saveDSPARB; uint32_t saveDSPARB;
uint32_t saveDSPATILEOFF;
uint32_t saveDSPBTILEOFF;
uint32_t saveDSPAADDR;
uint32_t saveDSPBADDR;
uint32_t savePFIT_AUTO_RATIOS; uint32_t savePFIT_AUTO_RATIOS;
uint32_t savePFIT_PGM_RATIOS; uint32_t savePFIT_PGM_RATIOS;
uint32_t savePP_ON_DELAYS; uint32_t savePP_ON_DELAYS;
...@@ -354,8 +340,6 @@ struct psb_state { ...@@ -354,8 +340,6 @@ struct psb_state {
uint32_t savePP_DIVISOR; uint32_t savePP_DIVISOR;
uint32_t saveBCLRPAT_A; uint32_t saveBCLRPAT_A;
uint32_t saveBCLRPAT_B; uint32_t saveBCLRPAT_B;
uint32_t saveDSPALINOFF;
uint32_t saveDSPBLINOFF;
uint32_t savePERF_MODE; uint32_t savePERF_MODE;
uint32_t saveDSPFW1; uint32_t saveDSPFW1;
uint32_t saveDSPFW2; uint32_t saveDSPFW2;
...@@ -370,8 +354,6 @@ struct psb_state { ...@@ -370,8 +354,6 @@ struct psb_state {
uint32_t saveDSPBCURSOR_BASE; uint32_t saveDSPBCURSOR_BASE;
uint32_t saveDSPACURSOR_POS; uint32_t saveDSPACURSOR_POS;
uint32_t saveDSPBCURSOR_POS; uint32_t saveDSPBCURSOR_POS;
uint32_t save_palette_a[256];
uint32_t save_palette_b[256];
uint32_t saveOV_OVADD; uint32_t saveOV_OVADD;
uint32_t saveOV_OGAMC0; uint32_t saveOV_OGAMC0;
uint32_t saveOV_OGAMC1; uint32_t saveOV_OGAMC1;
...@@ -394,64 +376,7 @@ struct psb_state { ...@@ -394,64 +376,7 @@ struct psb_state {
}; };
struct medfield_state { struct medfield_state {
uint32_t saveDPLL_A;
uint32_t saveFPA0;
uint32_t savePIPEACONF;
uint32_t saveHTOTAL_A;
uint32_t saveHBLANK_A;
uint32_t saveHSYNC_A;
uint32_t saveVTOTAL_A;
uint32_t saveVBLANK_A;
uint32_t saveVSYNC_A;
uint32_t savePIPEASRC;
uint32_t saveDSPASTRIDE;
uint32_t saveDSPALINOFF;
uint32_t saveDSPATILEOFF;
uint32_t saveDSPASIZE;
uint32_t saveDSPAPOS;
uint32_t saveDSPASURF;
uint32_t saveDSPACNTR;
uint32_t saveDSPASTATUS;
uint32_t save_palette_a[256];
uint32_t saveMIPI; uint32_t saveMIPI;
uint32_t saveDPLL_B;
uint32_t saveFPB0;
uint32_t savePIPEBCONF;
uint32_t saveHTOTAL_B;
uint32_t saveHBLANK_B;
uint32_t saveHSYNC_B;
uint32_t saveVTOTAL_B;
uint32_t saveVBLANK_B;
uint32_t saveVSYNC_B;
uint32_t savePIPEBSRC;
uint32_t saveDSPBSTRIDE;
uint32_t saveDSPBLINOFF;
uint32_t saveDSPBTILEOFF;
uint32_t saveDSPBSIZE;
uint32_t saveDSPBPOS;
uint32_t saveDSPBSURF;
uint32_t saveDSPBCNTR;
uint32_t saveDSPBSTATUS;
uint32_t save_palette_b[256];
uint32_t savePIPECCONF;
uint32_t saveHTOTAL_C;
uint32_t saveHBLANK_C;
uint32_t saveHSYNC_C;
uint32_t saveVTOTAL_C;
uint32_t saveVBLANK_C;
uint32_t saveVSYNC_C;
uint32_t savePIPECSRC;
uint32_t saveDSPCSTRIDE;
uint32_t saveDSPCLINOFF;
uint32_t saveDSPCTILEOFF;
uint32_t saveDSPCSIZE;
uint32_t saveDSPCPOS;
uint32_t saveDSPCSURF;
uint32_t saveDSPCCNTR;
uint32_t saveDSPCSTATUS;
uint32_t save_palette_c[256];
uint32_t saveMIPI_C; uint32_t saveMIPI_C;
uint32_t savePFIT_CONTROL; uint32_t savePFIT_CONTROL;
...@@ -480,6 +405,7 @@ struct cdv_state { ...@@ -480,6 +405,7 @@ struct cdv_state {
}; };
struct psb_save_area { struct psb_save_area {
struct psb_pipe pipe[3];
uint32_t saveBSM; uint32_t saveBSM;
uint32_t saveVBT; uint32_t saveVBT;
union { union {
......
drivers/gpu/drm/gma500/psb_intel_display.c
View file @ 6256304b
...@@ -799,8 +799,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ...@@ -799,8 +799,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
void psb_intel_crtc_load_lut(struct drm_crtc *crtc) void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_psb_private *dev_priv = struct drm_psb_private *dev_priv = dev->dev_private;
(struct drm_psb_private *)dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int palreg = PALETTE_A; int palreg = PALETTE_A;
int i; int i;
...@@ -836,7 +835,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc) ...@@ -836,7 +835,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
gma_power_end(dev); gma_power_end(dev);
} else { } else {
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
dev_priv->regs.psb.save_palette_a[i] = dev_priv->regs.pipe[0].palette[i] =
((psb_intel_crtc->lut_r[i] + ((psb_intel_crtc->lut_r[i] +
psb_intel_crtc->lut_adj[i]) << 16) | psb_intel_crtc->lut_adj[i]) << 16) |
((psb_intel_crtc->lut_g[i] + ((psb_intel_crtc->lut_g[i] +
...@@ -1121,6 +1120,7 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, ...@@ -1121,6 +1120,7 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
struct psb_intel_clock_t clock; struct psb_intel_clock_t clock;
bool is_lvds; bool is_lvds;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
...@@ -1131,18 +1131,12 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, ...@@ -1131,18 +1131,12 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
dpll = (pipe == 0) ? dpll = p->dpll;
dev_priv->regs.psb.saveDPLL_A :
dev_priv->regs.psb.saveDPLL_B;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = (pipe == 0) ? fp = p->fp0;
dev_priv->regs.psb.saveFPA0 :
dev_priv->regs.psb.saveFPB0;
else else
fp = (pipe == 0) ? fp = p->fp1;
dev_priv->regs.psb.saveFPA1 :
dev_priv->regs.psb.saveFPB1;
is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
LVDS_PORT_EN); LVDS_PORT_EN);
...@@ -1202,6 +1196,7 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, ...@@ -1202,6 +1196,7 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
int vtot; int vtot;
int vsync; int vsync;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
...@@ -1210,18 +1205,10 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, ...@@ -1210,18 +1205,10 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
htot = (pipe == 0) ? htot = p->htotal;
dev_priv->regs.psb.saveHTOTAL_A : hsync = p->hsync;
dev_priv->regs.psb.saveHTOTAL_B; vtot = p->vtotal;
hsync = (pipe == 0) ? vsync = p->vsync;
dev_priv->regs.psb.saveHSYNC_A :
dev_priv->regs.psb.saveHSYNC_B;
vtot = (pipe == 0) ?
dev_priv->regs.psb.saveVTOTAL_A :
dev_priv->regs.psb.saveVTOTAL_B;
vsync = (pipe == 0) ?
dev_priv->regs.psb.saveVSYNC_A :
dev_priv->regs.psb.saveVSYNC_B;
} }
mode = kzalloc(sizeof(*mode), GFP_KERNEL); mode = kzalloc(sizeof(*mode), GFP_KERNEL);
......
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