Commit 6686ece1 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Jani Nikula

drm/i915/skl: Disable coarse power gating up until F0

There is conflicting info between E0 and F0 steppings
for this workarounds. Trust more authoritative source and
be conservative and extend also for F0.

This prevents numerous (>50) gpu hangs with SKL GT4e
during piglit run.

References: HSD: gen9lp/2134184
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-1-git-send-email-mika.kuoppala@intel.comSigned-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent dfaf37ba
...@@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev) ...@@ -4717,7 +4717,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
*/ */
if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
IS_SKL_REVID(dev, 0, SKL_REVID_E0))) IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
I915_WRITE(GEN9_PG_ENABLE, 0); I915_WRITE(GEN9_PG_ENABLE, 0);
else else
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
......
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