drm/i915/display: Handle fused off HDCP

HDCP could be fused off, so not all GEN9+ platforms will support it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: default avatarRamalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-2-jose.souza@intel.com
parent a20e26d8
...@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work) ...@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
{ {
/* PORT E doesn't have HDCP, and PORT F is disabled */ /* PORT E doesn't have HDCP, and PORT F is disabled */
return INTEL_GEN(dev_priv) >= 9 && port < PORT_E; return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
} }
static int static int
......
...@@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = { ...@@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
.has_logical_ring_preemption = 1, \ .has_logical_ring_preemption = 1, \
.display.has_csr = 1, \ .display.has_csr = 1, \
.has_gt_uc = 1, \ .has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \ .display.has_ipc = 1, \
.ddb_size = 896 .ddb_size = 896
...@@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { ...@@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.display.has_ddi = 1, \ .display.has_ddi = 1, \
.has_fpga_dbg = 1, \ .has_fpga_dbg = 1, \
.display.has_fbc = 1, \ .display.has_fbc = 1, \
.display.has_hdcp = 1, \
.display.has_psr = 1, \ .display.has_psr = 1, \
.has_runtime_pm = 1, \ .has_runtime_pm = 1, \
.display.has_csr = 1, \ .display.has_csr = 1, \
......
...@@ -7743,6 +7743,7 @@ enum { ...@@ -7743,6 +7743,7 @@ enum {
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
#define SKL_DFSM _MMIO(0x51000) #define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
......
...@@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) ...@@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
enabled_mask); enabled_mask);
else else
info->pipe_mask = enabled_mask; info->pipe_mask = enabled_mask;
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
info->display.has_hdcp = 0;
} }
/* Initialize slice/subslice/EU info */ /* Initialize slice/subslice/EU info */
......
...@@ -139,6 +139,7 @@ enum intel_ppgtt_type { ...@@ -139,6 +139,7 @@ enum intel_ppgtt_type {
func(has_dsb); \ func(has_dsb); \
func(has_fbc); \ func(has_fbc); \
func(has_gmch); \ func(has_gmch); \
func(has_hdcp); \
func(has_hotplug); \ func(has_hotplug); \
func(has_ipc); \ func(has_ipc); \
func(has_modular_fia); \ func(has_modular_fia); \
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment