Commit 7bf3d70e authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman

staging: mt7621-gpio: avoid custom irq_domain for gpio

Instead of create a custom irq_domain for this chip, use
'gpiochip_set_chained_irqchip' from GPIOLIB_IRQCHIP. It
is ok to call this function several times. We have to
manually mark the line with 'IRQF_SHARED' and then loop
over the three banks until you find a hit. There were
some problems with removing an irqchip like that but this
driver is a bool so it might work just fine. After this
changes the functions 'mediatek_gpio_to_irq' is not needed
anymore and also the 'gpio_irq_domain' field from the state
container. Instead of use the custom irq domain in the irq
handler use the associated domain from the gpio_chip in
'irq_find_mapping' function. Function 'mediatek_gpio_bank_probe'
has been moved a it to the botton to have all the irq related
functions together and avoid some forward declarations to resolve
some symbols along the code.
Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 368d97d6
......@@ -2,6 +2,7 @@ config GPIO_MT7621
bool "Mediatek GPIO Support"
depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
select GPIO_GENERIC
select GPIOLIB_IRQCHIP
select ARCH_REQUIRE_GPIOLIB
help
Say yes here to support the Mediatek SoC GPIO device
......@@ -8,7 +8,6 @@
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
......@@ -58,14 +57,12 @@ struct mtk_gc {
* @dev: device instance
* @gpio_membase: memory base address
* @gpio_irq: irq number from the device tree
* @gpio_irq_domain: irq domain for this chip
* @gc_map: array of the gpio chips
*/
struct mtk_data {
struct device *dev;
void __iomem *gpio_membase;
int gpio_irq;
struct irq_domain *gpio_irq_domain;
struct mtk_gc gc_map[MTK_BANK_CNT];
};
......@@ -95,98 +92,36 @@ mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
return gc->read_reg(gpio_data->gpio_membase + offset);
}
static int
mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
{
struct mtk_data *gpio_data = gpiochip_get_data(chip);
struct mtk_gc *rg = to_mediatek_gpio(chip);
return irq_create_mapping(gpio_data->gpio_irq_domain,
pin + (rg->bank * MTK_BANK_WIDTH));
}
static int
mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
{
struct mtk_data *gpio = dev_get_drvdata(&pdev->dev);
const __be32 *id = of_get_property(bank, "reg", NULL);
struct mtk_gc *rg;
void __iomem *dat, *set, *ctrl, *diro;
int ret;
if (!id || be32_to_cpu(*id) >= MTK_BANK_CNT)
return -EINVAL;
rg = &gpio->gc_map[be32_to_cpu(*id)];
memset(rg, 0, sizeof(*rg));
spin_lock_init(&rg->lock);
rg->chip.of_node = bank;
rg->bank = be32_to_cpu(*id);
dat = gpio->gpio_membase + GPIO_REG_DATA + (rg->bank * GPIO_BANK_WIDE);
set = gpio->gpio_membase + GPIO_REG_DSET + (rg->bank * GPIO_BANK_WIDE);
ctrl = gpio->gpio_membase + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_WIDE);
diro = gpio->gpio_membase + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_WIDE);
ret = bgpio_init(&rg->chip, &pdev->dev, 4,
dat, set, ctrl, diro, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "bgpio_init() failed\n");
return ret;
}
if (gpio->gpio_irq_domain)
rg->chip.to_irq = mediatek_gpio_to_irq;
ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n",
rg->chip.ngpio, ret);
return ret;
}
/* set polarity to low for all gpios */
mtk_gpio_w32(rg, GPIO_REG_POL, 0);
dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
return 0;
}
static void
mediatek_gpio_irq_handler(struct irq_desc *desc)
static irqreturn_t
mediatek_gpio_irq_handler(int irq, void *data)
{
struct mtk_data *gpio_data = irq_desc_get_handler_data(desc);
int i;
for (i = 0; i < MTK_BANK_CNT; i++) {
struct mtk_gc *rg = &gpio_data->gc_map[i];
unsigned long pending;
int bit;
if (!rg)
continue;
struct gpio_chip *gc = data;
struct mtk_gc *rg = to_mediatek_gpio(gc);
irqreturn_t ret = IRQ_NONE;
unsigned long pending;
int bit;
pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
if (pending) {
for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
u32 map = irq_find_mapping(gpio_data->gpio_irq_domain,
(MTK_BANK_WIDTH * i) + bit);
u32 map = irq_find_mapping(gc->irq.domain, bit);
generic_handle_irq(map);
mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
ret |= IRQ_HANDLED;
}
}
return ret;
}
static void
mediatek_gpio_irq_unmask(struct irq_data *d)
{
struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
int bank = pin / MTK_BANK_WIDTH;
struct mtk_gc *rg = &gpio_data->gc_map[bank];
unsigned long flags;
u32 rise, fall, high, low;
......@@ -208,10 +143,9 @@ mediatek_gpio_irq_unmask(struct irq_data *d)
static void
mediatek_gpio_irq_mask(struct irq_data *d)
{
struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
int bank = pin / MTK_BANK_WIDTH;
struct mtk_gc *rg = &gpio_data->gc_map[bank];
unsigned long flags;
u32 rise, fall, high, low;
......@@ -233,10 +167,9 @@ mediatek_gpio_irq_mask(struct irq_data *d)
static int
mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct mtk_gc *rg = to_mediatek_gpio(gc);
int pin = d->hwirq;
int bank = pin / MTK_BANK_WIDTH;
struct mtk_gc *rg = &gpio_data->gc_map[bank];
u32 mask = PIN_MASK(pin);
if (!rg)
......@@ -277,65 +210,84 @@ mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
return 0;
}
static int mediatek_irq_reqres(struct irq_data *d)
{
struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
int bank = irqd_to_hwirq(d) / MTK_BANK_WIDTH;
struct mtk_gc *rg = &gpio_data->gc_map[bank];
struct gpio_chip *gc = &rg->chip;
int ret;
ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
if (ret) {
dev_err(gpio_data->dev, "unable to lock HW IRQ %lu for IRQ\n",
irqd_to_hwirq(d));
return -EINVAL;
}
return 0;
}
static void mediatek_irq_relres(struct irq_data *d)
{
struct mtk_data *gpio_data = irq_data_get_irq_chip_data(d);
int bank = irqd_to_hwirq(d) / MTK_BANK_WIDTH;
struct mtk_gc *rg = &gpio_data->gc_map[bank];
struct gpio_chip *gc = &rg->chip;
gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
}
static struct irq_chip mediatek_gpio_irq_chip = {
.name = "GPIO",
.irq_unmask = mediatek_gpio_irq_unmask,
.irq_mask = mediatek_gpio_irq_mask,
.irq_mask_ack = mediatek_gpio_irq_mask,
.irq_set_type = mediatek_gpio_irq_type,
.irq_request_resources = mediatek_irq_reqres,
.irq_release_resources = mediatek_irq_relres,
};
static int
mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
{
struct mtk_data *gpio = dev_get_drvdata(&pdev->dev);
const __be32 *id = of_get_property(bank, "reg", NULL);
struct mtk_gc *rg;
void __iomem *dat, *set, *ctrl, *diro;
int ret;
ret = irq_set_chip_data(irq, d->host_data);
if (ret < 0)
if (!id || be32_to_cpu(*id) >= MTK_BANK_CNT)
return -EINVAL;
rg = &gpio->gc_map[be32_to_cpu(*id)];
memset(rg, 0, sizeof(*rg));
spin_lock_init(&rg->lock);
rg->chip.of_node = bank;
rg->bank = be32_to_cpu(*id);
dat = gpio->gpio_membase + GPIO_REG_DATA + (rg->bank * GPIO_BANK_WIDE);
set = gpio->gpio_membase + GPIO_REG_DSET + (rg->bank * GPIO_BANK_WIDE);
ctrl = gpio->gpio_membase + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_WIDE);
diro = gpio->gpio_membase + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_WIDE);
ret = bgpio_init(&rg->chip, &pdev->dev, 4,
dat, set, ctrl, diro, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "bgpio_init() failed\n");
return ret;
}
ret = devm_gpiochip_add_data(&pdev->dev, &rg->chip, gpio);
if (ret < 0) {
dev_err(&pdev->dev, "Could not register gpio %d, ret=%d\n",
rg->chip.ngpio, ret);
return ret;
}
/*
* Manually request the irq here instead of passing a flow-handler
* to gpiochip_set_chained_irqchip, because the irq is shared.
*/
ret = devm_request_irq(&pdev->dev, gpio->gpio_irq,
mediatek_gpio_irq_handler, IRQF_SHARED,
"mt7621", &rg->chip);
if (ret) {
dev_err(&pdev->dev, "Error requesting IRQ %d: %d\n",
gpio->gpio_irq, ret);
return ret;
irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip,
handle_level_irq);
irq_set_handler_data(irq, d);
}
ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip,
0, handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
return ret;
}
gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip,
gpio->gpio_irq, NULL);
/* set polarity to low for all gpios */
mtk_gpio_w32(rg, GPIO_REG_POL, 0);
dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
return 0;
}
static const struct irq_domain_ops irq_domain_ops = {
.xlate = irq_domain_xlate_twocell,
.map = mediatek_gpio_gpio_map,
};
static int
mediatek_gpio_probe(struct platform_device *pdev)
{
......@@ -352,14 +304,6 @@ mediatek_gpio_probe(struct platform_device *pdev)
return PTR_ERR(gpio_data->gpio_membase);
gpio_data->gpio_irq = irq_of_parse_and_map(np, 0);
if (gpio_data->gpio_irq) {
gpio_data->gpio_irq_domain = irq_domain_add_linear(np,
MTK_BANK_CNT * MTK_BANK_WIDTH,
&irq_domain_ops, gpio_data);
if (!gpio_data->gpio_irq_domain)
dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
}
gpio_data->dev = &pdev->dev;
platform_set_drvdata(pdev, gpio_data);
......@@ -367,11 +311,6 @@ mediatek_gpio_probe(struct platform_device *pdev)
if (of_device_is_compatible(bank, "mediatek,mt7621-gpio-bank"))
mediatek_gpio_bank_probe(pdev, bank);
if (gpio_data->gpio_irq_domain)
irq_set_chained_handler_and_data(gpio_data->gpio_irq,
mediatek_gpio_irq_handler,
gpio_data);
return 0;
}
......
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