drm/amdgpu: update golden setting/tiling table of tahiti

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

drivers/gpu/drm/amd/amdgpu/si.c

@@ -43,13 +43,14 @@
 
 static const u32 tahiti_golden_registers[] =
 {
+	0x17bc, 0x00000030, 0x00000011,
 	0x2684, 0x00010000, 0x00018208,
 	0x260c, 0xffffffff, 0x00000000,
 	0x260d, 0xf00fffff, 0x00000400,
 	0x260e, 0x0002021c, 0x00020200,
 	0x031e, 0x00000080, 0x00000000,
-	0x340c, 0x000300c0, 0x00800040,
-	0x360c, 0x000300c0, 0x00800040,
+	0x340c, 0x000000c0, 0x00800040,
+	0x360c, 0x000000c0, 0x00800040,
 	0x16ec, 0x000000f0, 0x00000070,
 	0x16f0, 0x00200000, 0x50100000,
 	0x1c0c, 0x31000311, 0x00000011,
@@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
 	0x22c4, 0x0000ff0f, 0x00000000,
 	0xa293, 0x07ffffff, 0x4e000000,
 	0xa0d4, 0x3f3f3fff, 0x2a00126a,
-	0x000c, 0x000000ff, 0x0040,
+	0x000c, 0xffffffff, 0x0040,
 	0x000d, 0x00000040, 0x00004040,
 	0x2440, 0x07ffffff, 0x03000000,
 	0x23a2, 0x01ff1f3f, 0x00000000,
@@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
 	0x2234, 0xffffffff, 0x000fff40,
 	0x2235, 0x0000001f, 0x00000010,
 	0x0504, 0x20000000, 0x20fffed8,
-	0x0570, 0x000c0fc0, 0x000c0400
+	0x0570, 0x000c0fc0, 0x000c0400,
+	0x052c, 0x0fffffff, 0xffffffff,
+	0x052d, 0x0fffffff, 0x0fffffff,
+	0x052e, 0x0fffffff, 0x0fffffff,
+	0x052f, 0x0fffffff, 0x0fffffff
 };
 
 static const u32 tahiti_golden_registers2[] =
@@ -83,12 +88,13 @@ static const u32 tahiti_golden_registers2[] =
 
 static const u32 tahiti_golden_rlc_registers[] =
 {
+	0x263e, 0xffffffff, 0x12011003,
 	0x3109, 0xffffffff, 0x00601005,
 	0x311f, 0xffffffff, 0x10104040,
 	0x3122, 0xffffffff, 0x0100000a,
 	0x30c5, 0xffffffff, 0x00000800,
 	0x30c3, 0xffffffff, 0x800000f4,
-	0x3d2a, 0xffffffff, 0x00000000
+	0x3d2a, 0x00000008, 0x00000000
 };
 
 static const u32 pitcairn_golden_registers[] =
@@ -513,18 +519,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
 	0x21c2, 0xffffffff, 0x00900100,
 	0x311e, 0xffffffff, 0x00000080,
 	0x3101, 0xffffffff, 0x0020003f,
-	0xc, 0xffffffff, 0x0000001c,
-	0xd, 0x000f0000, 0x000f0000,
-	0x583, 0xffffffff, 0x00000100,
-	0x409, 0xffffffff, 0x00000100,
-	0x40b, 0x00000101, 0x00000000,
-	0x82a, 0xffffffff, 0x00000104,
-	0x993, 0x000c0000, 0x000c0000,
-	0x992, 0x000c0000, 0x000c0000,
+	0x000c, 0xffffffff, 0x0000001c,
+	0x000d, 0x000f0000, 0x000f0000,
+	0x0583, 0xffffffff, 0x00000100,
+	0x0409, 0xffffffff, 0x00000100,
+	0x040b, 0x00000101, 0x00000000,
+	0x082a, 0xffffffff, 0x00000104,
+	0x0993, 0x000c0000, 0x000c0000,
+	0x0992, 0x000c0000, 0x000c0000,
 	0x1579, 0xff000fff, 0x00000100,
 	0x157a, 0x00000001, 0x00000001,
-	0xbd4, 0x00000001, 0x00000001,
-	0xc33, 0xc0000fff, 0x00000104,
+	0x0bd4, 0x00000001, 0x00000001,
+	0x0c33, 0xc0000fff, 0x00000104,
 	0x3079, 0x00000001, 0x00000001,
 	0x3430, 0xfffffff0, 0x00000100,
 	0x3630, 0xfffffff0, 0x00000100
@@ -1179,6 +1185,8 @@ static int si_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_HDP_MGCG;
 			adev->pg_flags = 0;
+		adev->external_rev_id = (adev->rev_id == 0) ? 1 :
+					(adev->rev_id == 1) ? 5 : 6;
 		break;
 	case CHIP_PITCAIRN:
 		adev->cg_flags =