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Commit 7ed609b0 authored by Alexandre Belloni's avatar Alexandre Belloni
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ARM: dts: at91: sama5d3: switch to new clock bindings 

Switch sama5d3 boards to the new PMC clock bindings.

This prevents the wb50n to use the out of spec rate for USART1.

Link: https://lore.kernel.org/r/20200110222744.1261464-1-alexandre.belloni@bootlin.comSigned-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent 8f3d9f35
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Showing with 56 additions and 487 deletions
arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
View file @ 7ed609b0
......@@ -62,7 +62,7 @@ &i2c0 {
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck2>;
clocks = <&pmc PMC_TYPE_SYSTEM 10>;
clock-names = "mclk";
};
};
......
arch/arm/boot/dts/at91-wb50n.dtsi
View file @ 7ed609b0
......@@ -46,10 +46,6 @@ &clk32k {
atmel,osc-bypass;
};
&usart1_clk {
atmel,clk-output-range = <0 132000000>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
......
arch/arm/boot/dts/sama5d3.dtsi
View file @ 7ed609b0
This diff is collapsed.
arch/arm/boot/dts/sama5d3_can.dtsi
View file @ 7ed609b0
......@@ -31,29 +31,13 @@ pinctrl_can1_rx_tx: can1_rx_tx {
};
pmc: pmc@fffffc00 {
periphck {
can0_clk: can0_clk {
#clock-cells = <0>;
reg = <40>;
atmel,clk-output-range = <0 83000000>;
};
can1_clk: can1_clk {
#clock-cells = <0>;
reg = <41>;
atmel,clk-output-range = <0 83000000>;
};
};
};
can0: can@f000c000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf000c000 0x300>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
clocks = <&can0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
clock-names = "can_clk";
status = "disabled";
};
......@@ -64,7 +48,7 @@ can1: can@f8010000 {
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
clocks = <&can1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "can_clk";
status = "disabled";
};
......
arch/arm/boot/dts/sama5d3_emac.dtsi
View file @ 7ed609b0
......@@ -31,12 +31,6 @@ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with
};
pmc: pmc@fffffc00 {
periphck {
macb1_clk: macb1_clk {
#clock-cells = <0>;
reg = <35>;
};
};
};
macb1: ethernet@f802c000 {
......@@ -45,7 +39,7 @@ macb1: ethernet@f802c000 {
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
clocks = <&macb1_clk>, <&macb1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>;
clock-names = "hclk", "pclk";
status = "disabled";
};
......
arch/arm/boot/dts/sama5d3_gmac.dtsi
View file @ 7ed609b0
......@@ -63,22 +63,13 @@ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
};
};
pmc: pmc@fffffc00 {
periphck {
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <34>;
};
};
};
macb0: ethernet@f0028000 {
compatible = "atmel,sama5d3-gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
clocks = <&macb0_clk>, <&macb0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>;
clock-names = "hclk", "pclk";
status = "disabled";
};
......
arch/arm/boot/dts/sama5d3_lcd.dtsi
View file @ 7ed609b0
......@@ -16,7 +16,7 @@ hlcdc: hlcdc@f0030000 {
compatible = "atmel,sama5d3-hlcdc";
reg = <0xf0030000 0x2000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
......@@ -192,23 +192,6 @@ AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD22 pin */
};
};
};
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk {
#clock-cells = <0>;
reg = <36>;
};
};
systemck {
lcdck: lcdck {
#clock-cells = <0>;
reg = <3>;
clocks = <&mck>;
};
};
};
};
};
};
arch/arm/boot/dts/sama5d3_mci2.dtsi
View file @ 7ed609b0
......@@ -30,15 +30,6 @@ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC13 periph A MCI2_DA2 with p
};
};
pmc: pmc@fffffc00 {
periphck {
mci2_clk: mci2_clk {
#clock-cells = <0>;
reg = <23>;
};
};
};
mmc2: mmc@f8004000 {
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
......@@ -47,7 +38,7 @@ mmc2: mmc@f8004000 {
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
clocks = <&mci2_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "mci_clk";
status = "disabled";
#address-cells = <1>;
......
arch/arm/boot/dts/sama5d3_tcb1.dtsi
View file @ 7ed609b0
......@@ -17,23 +17,13 @@ aliases {
ahb {
apb {
pmc: pmc@fffffc00 {
periphck {
tcb1_clk: tcb1_clk {
#clock-cells = <0>;
reg = <27>;
atmel,clk-output-range = <0 166000000>;
};
};
};
tcb1: timer@f8014000 {
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8014000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&tcb1_clk>, <&clk32k>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
};
......
arch/arm/boot/dts/sama5d3_uart.dtsi
View file @ 7ed609b0
......@@ -36,29 +36,13 @@ pinctrl_uart1: uart1-0 {
};
};
pmc: pmc@fffffc00 {
periphck {
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <16>;
atmel,clk-output-range = <0 83000000>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <17>;
atmel,clk-output-range = <0 83000000>;
};
};
};
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart0_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
......@@ -69,7 +53,7 @@ uart1: serial@f8028000 {
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart1_clk>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "usart";
status = "disabled";
};
......
arch/arm/boot/dts/sama5d3xmb.dtsi
View file @ 7ed609b0
......@@ -46,7 +46,7 @@ i2c0: i2c@f0014000 {
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck0>;
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
};
};
......@@ -60,9 +60,9 @@ ov2640: camera@30 {
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
clocks = <&pck1>;
clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <25000000>;
port {
......
arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
View file @ 7ed609b0
......@@ -45,7 +45,7 @@ i2c0: i2c@f0014000 {
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck0>;
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
};
};
......@@ -59,9 +59,9 @@ ov2640: camera@30 {
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
clocks = <&pck1>;
clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <25000000>;
port {
......
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