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Commit 7f388396 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (47 commits)
  Blackfin: bfin_spi.h: add MMR peripheral layout
  Blackfin: bfin_ppi.h: start a common PPI/EPPI header
  Blackfin: bfin_can.h: add missing VERSION/VERSION2 MMRs
  Blackfin: bf538: add missing SIC_RVECT define
  Blackfin: bf561: rewrite SICA_xxx to just SIC_xxx
  Blackfin: bf54x: add missing SIC_RVECT definition
  Blackfin: H8606: move 8250 irqflags to platform resources
  Blackfin: glue XIP/ROM kernel kconfigs
  Blackfin: update sparse flags for latest upstream changes
  Blackfin: coreb: update ioctl numbers
  Blackfin: coreb: add gpl module license
  Blackfin: bf518-ezkit: add ssm2603 codec resources
  Blackfin: bf51x/bf52x: fix 16/32bit SPORT MMR helpers
  Blackfin: tll6527m: new board port
  Blackfin: bf526-ezbrd/bf527-ezkit: add NAND partition for u-boot
  Blackfin: merge kernel init memory back into main memory region
  Blackfin: gpio: add peripheral group check
  Blackfin: dma: bf54x: add missing break for SPORT1 TX IRQ
  Blackfin: add new cacheflush syscall
  Blackfin: bf548-ezkit: increase u-boot partition size
  ...
parents 10f2a2b0 b9ac41e3
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arch/blackfin/Kconfig
View file @ 7f388396
......@@ -300,7 +300,7 @@ config BF_REV_0_1
config BF_REV_0_2
bool "0.2"
depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
config BF_REV_0_3
bool "0.3"
......@@ -356,7 +356,7 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
default y
config MEM_MT48H32M16LFCJ_75
......@@ -426,6 +426,7 @@ config CLKIN_HZ
default "25000000" # most people use this
default "27000000" if BFIN533_EZKIT
default "30000000" if BFIN561_EZKIT
default "24000000" if BFIN527_AD7160EVAL
help
The frequency of CLKIN crystal oscillator on the board in Hz.
Warning: This value should match the crystal on the board. Otherwise,
......@@ -463,6 +464,7 @@ config VCO_MULT
default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
default "25" if BFIN527_AD7160EVAL
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
......@@ -926,6 +928,12 @@ config ROMKERNEL
endchoice
# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
config XIP_KERNEL
bool
default y
depends on ROMKERNEL
source "mm/Kconfig"
config BFIN_GPTIMERS
......
arch/blackfin/Makefile
View file @ 7f388396
......@@ -101,9 +101,8 @@ KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
# - the l1_text attribute is Blackfin specific, so fake it out as used to kill warnings
CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__
CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
head-y := arch/$(ARCH)/kernel/init_task.o
......
arch/blackfin/configs/BF527-AD7160-EVAL_defconfig 0 → 100644
View file @ 7f388396
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
# CONFIG_ELF_CORE is not set
# CONFIG_AIO is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_PREEMPT=y
CONFIG_BF527=y
CONFIG_BF_REV_0_2=y
CONFIG_IRQ_TWI=7
CONFIG_IRQ_PORTH_INTA=7
CONFIG_IRQ_PORTH_INTB=7
CONFIG_BFIN527_AD7160EVAL=y
CONFIG_BF527_SPORT0_PORTF=y
CONFIG_BF527_UART1_PORTG=y
CONFIG_IRQ_USB_INT0=11
CONFIG_IRQ_USB_INT1=11
CONFIG_IRQ_USB_INT2=11
CONFIG_IRQ_USB_DMA=11
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
CONFIG_CLKIN_HZ=24000000
CONFIG_HZ_300=y
# CONFIG_CYCLES_CLOCKSOURCE is not set
CONFIG_IP_CHECKSUM_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_BFIN_GPTIMERS=y
CONFIG_C_CDPRIO=y
CONFIG_BANK_1=0x5554
CONFIG_BANK_3=0xFFC0
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_NET=y
CONFIG_UNIX=y
# CONFIG_WIRELESS is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_AD7160=y
CONFIG_TOUCHSCREEN_AD7160_FW=y
# CONFIG_SERIO is not set
# CONFIG_BFIN_DMA_INTERFACE is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_BFIN=y
CONFIG_SERIAL_BFIN_CONSOLE=y
CONFIG_SERIAL_BFIN_UART0=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_BFIN_OTP is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
CONFIG_SPI=y
CONFIG_SPI_BFIN=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_GADGET_MUSB_HDRC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VBUS_DRAW=500
CONFIG_USB_G_SERIAL=y
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_SECURITY=y
CONFIG_CRC_CCITT=m
arch/blackfin/configs/BF527-TLL6527M_defconfig 0 → 100644
View file @ 7f388396
CONFIG_EXPERIMENTAL=y
CONFIG_LOCALVERSION="DEV_0-1_pre2010"
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_ELF_CORE is not set
# CONFIG_FUTEX is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BF527=y
CONFIG_BF_REV_0_2=y
CONFIG_BFIN527_TLL6527M=y
CONFIG_BF527_UART1_PORTG=y
CONFIG_IRQ_USB_INT0=11
CONFIG_IRQ_USB_INT1=11
CONFIG_IRQ_USB_INT2=11
CONFIG_IRQ_USB_DMA=11
CONFIG_BOOT_LOAD=0x400000
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_SCHEDULE_L1 is not set
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
CONFIG_BFIN_GPTIMERS=y
CONFIG_DMA_UNCACHED_2M=y
CONFIG_C_CDPRIO=y
CONFIG_BANK_0=0xFFC2
CONFIG_BANK_1=0xFFC2
CONFIG_BANK_2=0xFFC2
CONFIG_BANK_3=0xFFC2
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_IRDA=m
CONFIG_IRLAN=m
CONFIG_IRCOMM=m
CONFIG_IRTTY_SIR=m
CONFIG_BFIN_SIR=m
CONFIG_BFIN_SIR0=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_GPIO_ADDR=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_BFIN_MAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_AD7879=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AD714X=y
CONFIG_INPUT_ADXL34X=y
# CONFIG_SERIO is not set
CONFIG_BFIN_PPI=m
CONFIG_BFIN_SIMPLE_TIMER=m
CONFIG_BFIN_SPORT=m
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_DEVKMEM is not set
CONFIG_BFIN_JTAG_COMM=m
CONFIG_SERIAL_BFIN=y
CONFIG_SERIAL_BFIN_CONSOLE=y
CONFIG_SERIAL_BFIN_UART1=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SMBUS=y
CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_BFIN_WDT=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
CONFIG_VIDEO_BLACKFIN_CAM=m
CONFIG_OV9655=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_6x11=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_SOC=y
CONFIG_SND_BF5XX_I2S=y
CONFIG_SND_BF5XX_SOC_SSM2602=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_BFIN=y
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_UTF8=m
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_MMRS=y
CONFIG_DEBUG_HWERR=y
CONFIG_EXACT_HWERR=y
CONFIG_DEBUG_DOUBLEFAULT=y
CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_SECURITY=y
CONFIG_CRYPTO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC7=m
arch/blackfin/include/asm/Kbuild
View file @ 7f388396
include include/asm-generic/Kbuild.asm
header-y += bfin_sport.h
header-y += cachectl.h
header-y += fixed_code.h
arch/blackfin/include/asm/bfin5xx_spi.h
View file @ 7f388396
......@@ -41,6 +41,25 @@
#define BIT_STU_SENDOVER 0x0001
#define BIT_STU_RECVFULL 0x0020
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
/*
* bfin spi registers layout
*/
struct bfin_spi_regs {
__BFP(ctl);
__BFP(flg);
__BFP(stat);
__BFP(tdbr);
__BFP(rdbr);
__BFP(baud);
__BFP(shadow);
};
#define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */
......
arch/blackfin/include/asm/bfin_can.h
View file @ 7f388396
......@@ -34,6 +34,7 @@ struct bfin_can_mask_regs {
};
struct bfin_can_channel_regs {
/* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
u16 data[8];
__BFP(dlc);
__BFP(tsv);
......@@ -83,16 +84,18 @@ struct bfin_can_regs {
__BFP(gif); /* offset 0x9c */
__BFP(control); /* offset 0xa0 */
__BFP(intr); /* offset 0xa4 */
u32 __pad3[1];
__BFP(version); /* offset 0xa8 */
__BFP(mbtd); /* offset 0xac */
__BFP(ewr); /* offset 0xb0 */
__BFP(esr); /* offset 0xb4 */
u32 __pad4[2];
u32 __pad3[2];
__BFP(ucreg); /* offset 0xc0 */
__BFP(uccnt); /* offset 0xc4 */
__BFP(ucrc); /* offset 0xc8 */
__BFP(uccnf); /* offset 0xcc */
u32 __pad5[12];
u32 __pad4[1];
__BFP(version2); /* offset 0xd4 */
u32 __pad5[10];
/*
* channel(mailbox) mask and message registers
......
arch/blackfin/include/asm/bfin_ppi.h 0 → 100644
View file @ 7f388396
/*
* bfin_ppi.h - interface to Blackfin PPIs
*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ASM_BFIN_PPI_H__
#define __ASM_BFIN_PPI_H__
#include <linux/types.h>
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
/*
* bfin ppi registers layout
*/
struct bfin_ppi_regs {
__BFP(control);
__BFP(status);
__BFP(count);
__BFP(delay);
__BFP(frame);
};
/*
* bfin eppi registers layout
*/
struct bfin_eppi_regs {
__BFP(status);
__BFP(hcount);
__BFP(hdelay);
__BFP(vcount);
__BFP(vdelay);
__BFP(frame);
__BFP(line);
__BFP(clkdiv);
u32 control;
u32 fs1w_hbl;
u32 fs1p_avpl;
u32 fs2w_lvb;
u32 fs2p_lavf;
u32 clip;
};
#endif
arch/blackfin/include/asm/cachectl.h 0 → 100644
View file @ 7f388396
/*
* based on the mips/cachectl.h
*
* Copyright 2010 Analog Devices Inc.
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
*
* Licensed under the GPL-2 or later.
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
/*
* Options for cacheflush system call
*/
#define ICACHE (1<<0) /* flush instruction cache */
#define DCACHE (1<<1) /* writeback and flush data cache */
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
#endif /* _ASM_CACHECTL */
arch/blackfin/include/asm/cdef_LPBlackfin.h
View file @ 7f388396
......@@ -172,16 +172,19 @@
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
#if 0
#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
#endif
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
#if ANOMALY_05000481
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#endif
/* Event/Interrupt Registers*/
#define bfin_read_EVT0() bfin_read32(EVT0)
......
arch/blackfin/include/asm/ptrace.h
View file @ 7f388396
......@@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child);
/* common code demands this function */
#define ptrace_disable(child) user_disable_single_step(child)
extern int is_user_addr_valid(struct task_struct *child,
unsigned long start, unsigned long len);
/*
* Get the address of the live pt_regs for the specified task.
* These are saved onto the top kernel stack when the process
......
arch/blackfin/include/asm/serial.h
View file @ 7f388396
#include <asm-generic/serial.h>
#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
arch/blackfin/include/asm/unistd.h
View file @ 7f388396
......@@ -392,8 +392,9 @@
#define __NR_fanotify_init 371
#define __NR_fanotify_mark 372
#define __NR_prlimit64 373
#define __NR_cacheflush 374
#define __NR_syscall 374
#define __NR_syscall 375
#define NR_syscalls __NR_syscall
/* Old optional stuff no one actually uses */
......
arch/blackfin/kernel/bfin_gpio.c
View file @ 7f388396
/*
* GPIO Abstraction Layer
*
* Copyright 2006-2009 Analog Devices Inc.
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
......@@ -215,82 +215,91 @@ static void port_setup(unsigned gpio, unsigned short usage)
}
#ifdef BF537_FAMILY
static struct {
unsigned short res;
unsigned short offset;
} port_mux_lut[] = {
{.res = P_PPI0_D13, .offset = 11},
{.res = P_PPI0_D14, .offset = 11},
{.res = P_PPI0_D15, .offset = 11},
{.res = P_SPORT1_TFS, .offset = 11},
{.res = P_SPORT1_TSCLK, .offset = 11},
{.res = P_SPORT1_DTPRI, .offset = 11},
{.res = P_PPI0_D10, .offset = 10},
{.res = P_PPI0_D11, .offset = 10},
{.res = P_PPI0_D12, .offset = 10},
{.res = P_SPORT1_RSCLK, .offset = 10},
{.res = P_SPORT1_RFS, .offset = 10},
{.res = P_SPORT1_DRPRI, .offset = 10},
{.res = P_PPI0_D8, .offset = 9},
{.res = P_PPI0_D9, .offset = 9},
{.res = P_SPORT1_DRSEC, .offset = 9},
{.res = P_SPORT1_DTSEC, .offset = 9},
{.res = P_TMR2, .offset = 8},
{.res = P_PPI0_FS3, .offset = 8},
{.res = P_TMR3, .offset = 7},
{.res = P_SPI0_SSEL4, .offset = 7},
{.res = P_TMR4, .offset = 6},
{.res = P_SPI0_SSEL5, .offset = 6},
{.res = P_TMR5, .offset = 5},
{.res = P_SPI0_SSEL6, .offset = 5},
{.res = P_UART1_RX, .offset = 4},
{.res = P_UART1_TX, .offset = 4},
{.res = P_TMR6, .offset = 4},
{.res = P_TMR7, .offset = 4},
{.res = P_UART0_RX, .offset = 3},
{.res = P_UART0_TX, .offset = 3},
{.res = P_DMAR0, .offset = 3},
{.res = P_DMAR1, .offset = 3},
{.res = P_SPORT0_DTSEC, .offset = 1},
{.res = P_SPORT0_DRSEC, .offset = 1},
{.res = P_CAN0_RX, .offset = 1},
{.res = P_CAN0_TX, .offset = 1},
{.res = P_SPI0_SSEL7, .offset = 1},
{.res = P_SPORT0_TFS, .offset = 0},
{.res = P_SPORT0_DTPRI, .offset = 0},
{.res = P_SPI0_SSEL2, .offset = 0},
{.res = P_SPI0_SSEL3, .offset = 0},
static const s8 port_mux[] = {
[GPIO_PF0] = 3,
[GPIO_PF1] = 3,
[GPIO_PF2] = 4,
[GPIO_PF3] = 4,
[GPIO_PF4] = 5,
[GPIO_PF5] = 6,
[GPIO_PF6] = 7,
[GPIO_PF7] = 8,
[GPIO_PF8 ... GPIO_PF15] = -1,
[GPIO_PG0 ... GPIO_PG7] = -1,
[GPIO_PG8] = 9,
[GPIO_PG9] = 9,
[GPIO_PG10] = 10,
[GPIO_PG11] = 10,
[GPIO_PG12] = 10,
[GPIO_PG13] = 11,
[GPIO_PG14] = 11,
[GPIO_PG15] = 11,
[GPIO_PH0 ... GPIO_PH15] = -1,
[PORT_PJ0 ... PORT_PJ3] = -1,
[PORT_PJ4] = 1,
[PORT_PJ5] = 1,
[PORT_PJ6 ... PORT_PJ9] = -1,
[PORT_PJ10] = 0,
[PORT_PJ11] = 0,
};
static void portmux_setup(unsigned short per)
static int portmux_group_check(unsigned short per)
{
u16 y, offset, muxreg;
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
s8 offset = port_mux[ident];
u16 m, pmux, pfunc;
for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
if (port_mux_lut[y].res == per) {
/* SET PORTMUX REG */
offset = port_mux_lut[y].offset;
muxreg = bfin_read_PORT_MUX();
if (offset < 0)
return 0;
if (offset != 1)
muxreg &= ~(1 << offset);
else
muxreg &= ~(3 << 1);
pmux = bfin_read_PORT_MUX();
for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
if (m == ident)
continue;
if (port_mux[m] != offset)
continue;
if (!is_reserved(peri, m, 1))
continue;
muxreg |= (function << offset);
bfin_write_PORT_MUX(muxreg);
if (offset == 1)
pfunc = (pmux >> offset) & 3;
else
pfunc = (pmux >> offset) & 1;
if (pfunc != function) {
pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
ident, function, m, pfunc);
return -EINVAL;
}
}
return 0;
}
static void portmux_setup(unsigned short per)
{
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
s8 offset = port_mux[ident];
u16 pmux;
if (offset == -1)
return;
pmux = bfin_read_PORT_MUX();
if (offset != 1)
pmux &= ~(1 << offset);
else
pmux &= ~(3 << 1);
pmux |= (function << offset);
bfin_write_PORT_MUX(pmux);
}
#elif defined(CONFIG_BF54x)
inline void portmux_setup(unsigned short per)
{
u32 pmux;
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
u32 pmux;
pmux = gpio_array[gpio_bank(ident)]->port_mux;
......@@ -302,20 +311,54 @@ inline void portmux_setup(unsigned short per)
inline u16 get_portmux(unsigned short per)
{
u32 pmux;
u16 ident = P_IDENT(per);
pmux = gpio_array[gpio_bank(ident)]->port_mux;
u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
}
static int portmux_group_check(unsigned short per)
{
return 0;
}
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
static int portmux_group_check(unsigned short per)
{
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
u16 pin, gpiopin, pfunc;
for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
if (offset != pmux_offset[gpio_bank(ident)][pin])
continue;
gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
if (gpiopin == ident)
continue;
if (!is_reserved(peri, gpiopin, 1))
continue;
pfunc = *port_mux[gpio_bank(ident)];
pfunc = (pfunc >> offset) & 3;
if (pfunc != function) {
pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
ident, function, gpiopin, pfunc);
return -EINVAL;
}
}
return 0;
}
inline void portmux_setup(unsigned short per)
{
u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
u16 ident = P_IDENT(per);
u16 function = P_FUNCT2MUX(per);
u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
u16 pmux;
pmux = *port_mux[gpio_bank(ident)];
if (((pmux >> offset) & 3) == function)
return;
pmux &= ~(3 << offset);
pmux |= (function & 3) << offset;
*port_mux[gpio_bank(ident)] = pmux;
......@@ -323,6 +366,10 @@ inline void portmux_setup(unsigned short per)
}
#else
# define portmux_setup(...) do { } while (0)
static int portmux_group_check(unsigned short per)
{
return 0;
}
#endif
#ifndef CONFIG_BF54x
......@@ -735,6 +782,10 @@ int peripheral_request(unsigned short per, const char *label)
}
}
if (unlikely(portmux_group_check(per))) {
hard_local_irq_restore(flags);
return -EBUSY;
}
anyway:
reserve(peri, ident);
......
arch/blackfin/kernel/process.c
View file @ 7f388396
......@@ -493,6 +493,11 @@ int _access_ok(unsigned long addr, unsigned long size)
return 1;
#endif
#ifndef CONFIG_EXCEPTION_L1_SCRATCH
if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
return 1;
#endif
aret = in_async(addr, size);
if (aret < 2)
return aret;
......
arch/blackfin/kernel/ptrace.c
View file @ 7f388396
......@@ -27,6 +27,7 @@
#include <asm/fixed_code.h>
#include <asm/cacheflush.h>
#include <asm/mem_map.h>
#include <asm/mmu_context.h>
/*
* does not yet catch signals sent when the child dies.
......@@ -113,8 +114,8 @@ put_reg(struct task_struct *task, long regno, unsigned long data)
/*
* check that an address falls within the bounds of the target process's memory mappings
*/
static inline int is_user_addr_valid(struct task_struct *child,
unsigned long start, unsigned long len)
int
is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
{
struct vm_area_struct *vma;
struct sram_list_struct *sraml;
......@@ -135,6 +136,13 @@ static inline int is_user_addr_valid(struct task_struct *child,
if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
return 0;
#ifdef CONFIG_APP_STACK_L1
if (child->mm->context.l1_stack_save)
if (start >= (unsigned long)l1_stack_base &&
start + len < (unsigned long)l1_stack_base + l1_stack_len)
return 0;
#endif
return -EIO;
}
......
arch/blackfin/kernel/sys_bfin.c
View file @ 7f388396
......@@ -21,6 +21,8 @@
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/cachectl.h>
#include <asm/ptrace.h>
asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
{
......@@ -70,3 +72,16 @@ asmlinkage int sys_bfin_spinlock(int *p)
return ret;
}
SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
{
if (is_user_addr_valid(current, addr, len) != 0)
return -EINVAL;
if (op & DCACHE)
blackfin_dcache_flush_range(addr, addr + len);
if (op & ICACHE)
blackfin_icache_flush_range(addr, addr + len);
return 0;
}
arch/blackfin/mach-bf518/boards/ezbrd.c
View file @ 7f388396
......@@ -312,7 +312,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* SPI (0) */
static struct bfin5xx_spi_master bfin_spi0_info = {
.num_chipselect = 5,
.num_chipselect = 6,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
......@@ -347,7 +347,7 @@ static struct platform_device bfin_spi0_device = {
/* SPI (1) */
static struct bfin5xx_spi_master bfin_spi1_info = {
.num_chipselect = 5,
.num_chipselect = 6,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
......@@ -525,6 +525,14 @@ static struct platform_device bfin_sir1_device = {
#endif
#endif
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
/* TODO: add platform data here */
};
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
......@@ -559,6 +567,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
.irq = IRQ_PF8,
},
#endif
#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
{
I2C_BOARD_INFO("ssm2602", 0x1b),
},
#endif
};
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
......@@ -736,6 +749,10 @@ static struct platform_device *stamp_devices[] __initdata = {
&i2c_bfin_twi_device,
#endif
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
&bfin_sport0_uart_device,
......
arch/blackfin/mach-bf518/boards/tcm-bf518.c
View file @ 7f388396
......@@ -291,7 +291,7 @@ static struct platform_device bfin_spi0_device = {
/* SPI (1) */
static struct bfin5xx_spi_master bfin_spi1_info = {
.num_chipselect = 5,
.num_chipselect = 6,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
......
arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
View file @ 7f388396
......@@ -262,14 +262,14 @@
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
......@@ -317,14 +317,14 @@
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
......
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View file @ 7f388396
......@@ -748,51 +748,6 @@
#define FFE 0x20 /* Force Framing Error On Transmit */
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
/* SPI_CTL Masks */
#define TIMOD 0x0003 /* Transfer Initiate Mode */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
#define PSSE 0x0010 /* Slave-Select Input Enable */
#define EMISO 0x0020 /* Enable MISO As Output */
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
#define LSBF 0x0200 /* LSB First */
#define CPHA 0x0400 /* Clock Phase */
#define CPOL 0x0800 /* Clock Polarity */
#define MSTR 0x1000 /* Master/Slave* */
#define WOM 0x2000 /* Write Open Drain Master */
#define SPE 0x4000 /* SPI Enable */
/* SPI_FLG Masks */
#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
/* SPI_STAT Masks */
#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
/* **************** GENERAL PURPOSE TIMER MASKS **********************/
/* TIMER_ENABLE Masks */
#define TIMEN0 0x0001 /* Enable Timer 0 */
......
arch/blackfin/mach-bf527/boards/Kconfig
View file @ 7f388396
......@@ -24,4 +24,14 @@ config BFIN526_EZBRD
help
BF526-EZBRD/EZKIT Lite board support.
config BFIN527_AD7160EVAL
bool "BF527-AD7160-EVAL"
help
BF527-AD7160-EVAL board support.
config BFIN527_TLL6527M
bool "The Learning Labs TLL6527M"
help
TLL6527M V1.0 platform support
endchoice
arch/blackfin/mach-bf527/boards/Makefile
View file @ 7f388396
......@@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
arch/blackfin/mach-bf527/boards/ad7160eval.c 0 → 100644
View file @ 7f388396
This diff is collapsed.
arch/blackfin/mach-bf527/boards/cm_bf527.c
View file @ 7f388396
......@@ -342,8 +342,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -420,13 +420,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......
arch/blackfin/mach-bf527/boards/ezbrd.c
View file @ 7f388396
......@@ -137,8 +137,12 @@ static struct platform_device ezbrd_flash_device = {
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.name = "bootloader(nand)",
.offset = 0,
.size = 0x40000,
}, {
.name = "linux kernel(nand)",
.offset = MTDPART_OFS_APPEND,
.size = 4 * 1024 * 1024,
},
{
......
arch/blackfin/mach-bf527/boards/ezkit.c
View file @ 7f388396
......@@ -222,8 +222,12 @@ static struct platform_device ezkit_flash_device = {
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.name = "bootloader(nand)",
.offset = 0,
.size = 0x40000,
}, {
.name = "linux kernel(nand)",
.offset = MTDPART_OFS_APPEND,
.size = 4 * 1024 * 1024,
},
{
......@@ -431,8 +435,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -547,13 +551,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -929,6 +933,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
I2C_BOARD_INFO("ssm2602", 0x1b),
},
#endif
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("ad5252", 0x2f),
},
#endif
};
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
......
arch/blackfin/mach-bf527/boards/tll6527m.c 0 → 100644
View file @ 7f388396
This diff is collapsed.
arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
View file @ 7f388396
......@@ -279,14 +279,14 @@
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
......@@ -334,14 +334,14 @@
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
......
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View file @ 7f388396
......@@ -749,51 +749,6 @@
#define FFE 0x20 /* Force Framing Error On Transmit */
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
/* SPI_CTL Masks */
#define TIMOD 0x0003 /* Transfer Initiate Mode */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
#define PSSE 0x0010 /* Slave-Select Input Enable */
#define EMISO 0x0020 /* Enable MISO As Output */
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
#define LSBF 0x0200 /* LSB First */
#define CPHA 0x0400 /* Clock Phase */
#define CPOL 0x0800 /* Clock Polarity */
#define MSTR 0x1000 /* Master/Slave* */
#define WOM 0x2000 /* Write Open Drain Master */
#define SPE 0x4000 /* SPI Enable */
/* SPI_FLG Masks */
#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
/* SPI_STAT Masks */
#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
/* **************** GENERAL PURPOSE TIMER MASKS **********************/
/* TIMER_ENABLE Masks */
#define TIMEN0 0x0001 /* Enable Timer 0 */
......
arch/blackfin/mach-bf533/boards/H8606.c
View file @ 7f388396
......@@ -171,7 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -206,12 +206,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 16,
.bus_num = 1,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -347,6 +347,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
.membase = (void *)0x20200000,
.mapbase = 0x20200000,
.irq = IRQ_PF8,
.irqflags = IRQF_TRIGGER_HIGH,
.flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
.iotype = UPIO_MEM,
.regshift = 1,
......@@ -355,6 +356,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
.membase = (void *)0x20200010,
.mapbase = 0x20200010,
.irq = IRQ_PF8,
.irqflags = IRQF_TRIGGER_HIGH,
.flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
.iotype = UPIO_MEM,
.regshift = 1,
......
arch/blackfin/mach-bf533/boards/blackstamp.c
View file @ 7f388396
......@@ -368,8 +368,8 @@ static struct platform_device bfin_device_gpiokeys = {
#include <linux/i2c-gpio.h>
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = 8,
.scl_pin = 9,
.sda_pin = GPIO_PF8,
.scl_pin = GPIO_PF9,
.sda_is_open_drain = 0,
.scl_is_open_drain = 0,
.udelay = 40,
......
arch/blackfin/mach-bf533/boards/cm_bf533.c
View file @ 7f388396
......@@ -71,7 +71,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -110,12 +110,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -400,7 +400,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PF4,
.end = IRQ_PF4,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf533/boards/ezkit.c
View file @ 7f388396
......@@ -222,7 +222,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -261,12 +261,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -422,8 +422,8 @@ static struct platform_device bfin_device_gpiokeys = {
#include <linux/i2c-gpio.h>
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = 1,
.scl_pin = 0,
.sda_pin = GPIO_PF1,
.scl_pin = GPIO_PF0,
.sda_is_open_drain = 0,
.scl_is_open_drain = 0,
.udelay = 40,
......
arch/blackfin/mach-bf533/boards/ip0x.c
View file @ 7f388396
......@@ -232,7 +232,7 @@ static struct resource isp1362_hcd_resources[] = {
},{
.start = IRQ_PF11,
.end = IRQ_PF11,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf533/boards/stamp.c
View file @ 7f388396
......@@ -185,7 +185,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -252,13 +252,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.platform_data = "ad1836", /* only includes chip name for the moment */
.controller_data = &ad1836_spi_chip_info,
.mode = SPI_MODE_3,
},
#endif
......@@ -495,8 +497,8 @@ static struct platform_device bfin_device_gpiokeys = {
#include <linux/i2c-gpio.h>
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = 2,
.scl_pin = 3,
.sda_pin = GPIO_PF2,
.scl_pin = GPIO_PF3,
.sda_is_open_drain = 0,
.scl_is_open_drain = 0,
.udelay = 40,
......@@ -534,6 +536,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
I2C_BOARD_INFO("bfin-adv7393", 0x2B),
},
#endif
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("ad5252", 0x2f),
},
#endif
};
static const unsigned int cclk_vlev_datasheet[] =
......
arch/blackfin/mach-bf533/include/mach/defBF532.h
View file @ 7f388396
......@@ -681,76 +681,6 @@
#define PF14_P 14
#define PF15_P 15
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
/* SPI_CTL Masks */
#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
/* SPI_FLG Masks */
#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPI_FLG Bit Positions */
#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPI_STAT Masks */
#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
/* SPIx_FLG Masks */
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
/* AMGCTL Masks */
......
arch/blackfin/mach-bf537/Kconfig
View file @ 7f388396
......@@ -14,8 +14,8 @@ config IRQ_DMA_ERROR
int "IRQ_DMA_ERROR Generic"
default 7
config IRQ_ERROR
int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
default 7
int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
default 11
config IRQ_RTC
int "IRQ_RTC"
default 8
......
arch/blackfin/mach-bf537/boards/cm_bf537e.c
View file @ 7f388396
......@@ -73,7 +73,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -112,12 +112,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -229,7 +229,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PG15,
.end = IRQ_PG15,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf537/boards/cm_bf537u.c
View file @ 7f388396
......@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PG15,
.end = IRQ_PG15,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf537/boards/pnav10.c
View file @ 7f388396
......@@ -175,8 +175,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -238,13 +238,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......
arch/blackfin/mach-bf537/boards/stamp.c
View file @ 7f388396
This diff is collapsed.
arch/blackfin/mach-bf537/boards/tcm_bf537.c
View file @ 7f388396
......@@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PG15,
.end = IRQ_PG15,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf537/include/mach/defBF534.h
View file @ 7f388396
......@@ -1071,50 +1071,6 @@
#define FPE 0x10 /* Force Parity Error On Transmit */
#define FFE 0x20 /* Force Framing Error On Transmit */
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
/* SPI_CTL Masks */
#define TIMOD 0x0003 /* Transfer Initiate Mode */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
#define PSSE 0x0010 /* Slave-Select Input Enable */
#define EMISO 0x0020 /* Enable MISO As Output */
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
#define LSBF 0x0200 /* LSB First */
#define CPHA 0x0400 /* Clock Phase */
#define CPOL 0x0800 /* Clock Polarity */
#define MSTR 0x1000 /* Master/Slave* */
#define WOM 0x2000 /* Write Open Drain Master */
#define SPE 0x4000 /* SPI Enable */
/* SPI_FLG Masks */
#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
/* SPI_STAT Masks */
#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
/* **************** GENERAL PURPOSE TIMER MASKS **********************/
/* TIMER_ENABLE Masks */
#define TIMEN0 0x0001 /* Enable Timer 0 */
......
arch/blackfin/mach-bf538/boards/ezkit.c
View file @ 7f388396
......@@ -695,7 +695,7 @@ static struct platform_device bf538_spi_master0 = {
};
static struct bfin5xx_spi_master bf538_spi_master_info1 = {
.num_chipselect = 8,
.num_chipselect = 2,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
......@@ -711,7 +711,7 @@ static struct platform_device bf538_spi_master1 = {
};
static struct bfin5xx_spi_master bf538_spi_master_info2 = {
.num_chipselect = 8,
.num_chipselect = 2,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
};
......
arch/blackfin/mach-bf538/include/mach/defBF539.h
View file @ 7f388396
......@@ -32,6 +32,7 @@
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration registe */
#define SIC_RVECT 0xFFC00108
#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
......@@ -1894,78 +1895,6 @@
#define PE14_P 0xE
#define PE15_P 0xF
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
/* SPIx_CTL Masks */
#define TIMOD 0x0003 /* Transfer Initiate Mode */
#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
#define PSSE 0x0010 /* Slave-Select Input Enable */
#define EMISO 0x0020 /* Enable MISO As Output */
#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
#define LSBF 0x0200 /* LSB First */
#define CPHA 0x0400 /* Clock Phase */
#define CPOL 0x0800 /* Clock Polarity */
#define MSTR 0x1000 /* Master/Slave* */
#define WOM 0x2000 /* Write Open Drain Master */
#define SPE 0x4000 /* SPI Enable */
/* SPIx_FLG Masks */
#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPIx_FLG Bit Positions */
#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPIx_STAT Masks */
#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
/* SPIx_FLG Masks */
#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
/* EBIU_AMGCTL Masks */
#define AMCKEN 0x0001 /* Enable CLKOUT */
......
arch/blackfin/mach-bf548/boards/cm_bf548.c
View file @ 7f388396
......@@ -753,6 +753,44 @@ static struct platform_device bf54x_sdh_device = {
};
#endif
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
unsigned short bfin_can_peripherals[] = {
P_CAN0_RX, P_CAN0_TX, 0
};
static struct resource bfin_can_resources[] = {
{
.start = 0xFFC02A00,
.end = 0xFFC02FFF,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_CAN0_RX,
.end = IRQ_CAN0_RX,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_CAN0_TX,
.end = IRQ_CAN0_TX,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_CAN0_ERROR,
.end = IRQ_CAN0_ERROR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_can_device = {
.name = "bfin_can",
.num_resources = ARRAY_SIZE(bfin_can_resources),
.resource = bfin_can_resources,
.dev = {
.platform_data = &bfin_can_peripherals, /* Passed to driver */
},
};
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition para_partitions[] = {
{
......@@ -928,7 +966,7 @@ static struct resource bfin_spi1_resource[] = {
/* SPI controller data */
static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
.num_chipselect = 3,
.num_chipselect = 4,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
......@@ -944,7 +982,7 @@ static struct platform_device bf54x_spi_master0 = {
};
static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
.num_chipselect = 3,
.num_chipselect = 4,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
......@@ -1152,6 +1190,11 @@ static struct platform_device *cm_bf548_devices[] __initdata = {
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&para_flash_device,
#endif
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
&bfin_can_device,
#endif
};
static int __init cm_bf548_init(void)
......
arch/blackfin/mach-bf548/boards/ezkit.c
View file @ 7f388396
......@@ -837,8 +837,12 @@ static struct platform_device bfin_atapi_device = {
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.name = "bootloader(nand)",
.offset = 0,
.size = 0x80000,
}, {
.name = "linux kernel(nand)",
.offset = MTDPART_OFS_APPEND,
.size = 4 * 1024 * 1024,
},
{
......@@ -901,7 +905,7 @@ static struct platform_device bf54x_sdh_device = {
static struct mtd_partition ezkit_partitions[] = {
{
.name = "bootloader(nor)",
.size = 0x40000,
.size = 0x80000,
.offset = 0,
}, {
.name = "linux kernel(nor)",
......@@ -943,7 +947,7 @@ static struct platform_device ezkit_flash_device = {
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
.name = "bootloader(spi)",
.size = 0x00040000,
.size = 0x00080000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
......@@ -966,8 +970,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -1023,13 +1027,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -1107,7 +1111,7 @@ static struct resource bfin_spi1_resource[] = {
/* SPI controller data */
static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
.num_chipselect = 3,
.num_chipselect = 4,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
......@@ -1123,7 +1127,7 @@ static struct platform_device bf54x_spi_master0 = {
};
static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
.num_chipselect = 3,
.num_chipselect = 4,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
......@@ -1206,6 +1210,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
.platform_data = (void *)&adxl34x_info,
},
#endif
#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("ad5252", 0x2f),
},
#endif
};
#endif
......
arch/blackfin/mach-bf548/dma.c
View file @ 7f388396
......@@ -63,6 +63,7 @@ int channel2irq(unsigned int channel)
break;
case CH_SPORT1_TX:
ret_irq = IRQ_SPORT1_TX;
break;
case CH_SPI0:
ret_irq = IRQ_SPI0;
break;
......
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
View file @ 7f388396
......@@ -40,6 +40,8 @@
/* SIC Registers */
#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
......
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View file @ 7f388396
......@@ -35,6 +35,7 @@
/* SIC Registers */
#define SIC_RVECT 0xffc00108
#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
......@@ -2061,56 +2062,6 @@
#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
/* Bit masks for SPIx_BAUD */
#define SPI_BAUD 0xffff /* Baud Rate */
/* Bit masks for SPIx_CTL */
#define SPE 0x4000 /* SPI Enable */
#define WOM 0x2000 /* Write Open Drain Master */
#define MSTR 0x1000 /* Master Mode */
#define CPOL 0x800 /* Clock Polarity */
#define CPHA 0x400 /* Clock Phase */
#define LSBF 0x200 /* LSB First */
#define SIZE 0x100 /* Size of Words */
#define EMISO 0x20 /* Enable MISO Output */
#define PSSE 0x10 /* Slave-Select Enable */
#define GM 0x8 /* Get More Data */
#define SZ 0x4 /* Send Zero */
#define TIMOD 0x3 /* Transfer Initiation Mode */
/* Bit masks for SPIx_FLG */
#define FLS1 0x2 /* Slave Select Enable 1 */
#define FLS2 0x4 /* Slave Select Enable 2 */
#define FLS3 0x8 /* Slave Select Enable 3 */
#define FLG1 0x200 /* Slave Select Value 1 */
#define FLG2 0x400 /* Slave Select Value 2 */
#define FLG3 0x800 /* Slave Select Value 3 */
/* Bit masks for SPIx_STAT */
#define TXCOL 0x40 /* Transmit Collision Error */
#define RXS 0x20 /* RDBR Data Buffer Status */
#define RBSY 0x10 /* Receive Error */
#define TXS 0x8 /* TDBR Data Buffer Status */
#define TXE 0x4 /* Transmission Error */
#define MODF 0x2 /* Mode Fault Error */
#define SPIF 0x1 /* SPI Finished */
/* Bit masks for SPIx_TDBR */
#define TDBR 0xffff /* Transmit Data Buffer */
/* Bit masks for SPIx_RDBR */
#define RDBR 0xffff /* Receive Data Buffer */
/* Bit masks for SPIx_SHADOW */
#define SHADOW 0xffff /* RDBR Shadow */
/* ************************************************ */
/* The TWI bit masks fields are from the ADSP-BF538 */
/* and they have not been verified as the final */
......
arch/blackfin/mach-bf561/boards/acvilon.c
View file @ 7f388396
......@@ -302,7 +302,7 @@ static struct platform_nand_data bfin_plat_nand_data = {
static struct resource bfin_plat_nand_resources = {
.start = 0x24000000,
.end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
.flags = IORESOURCE_IO,
.flags = IORESOURCE_MEM,
};
static struct platform_device bfin_async_nand_device = {
......
arch/blackfin/mach-bf561/boards/cm_bf561.c
View file @ 7f388396
......@@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.controller_data = &ad1836_spi_chip_info,
},
#endif
......@@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PF47,
.end = IRQ_PF47,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......
arch/blackfin/mach-bf561/boards/ezkit.c
View file @ 7f388396
......@@ -14,6 +14,7 @@
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
......@@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = {
}, {
.start = IRQ_PF8,
.end = IRQ_PF8,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
......@@ -274,8 +275,8 @@ static struct platform_device ezkit_flash_device = {
};
#endif
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
......@@ -328,14 +329,16 @@ static struct platform_device bfin_spi0_device = {
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SND_BLACKFIN_AD183X) \
|| defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
|| defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
{
.modalias = "ad1836",
.modalias = "ad183x",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
.chip_select = 4,
.platform_data = "ad1836", /* only includes chip name for the moment */
.controller_data = &ad1836_spi_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
......@@ -377,8 +380,8 @@ static struct platform_device bfin_device_gpiokeys = {
#include <linux/i2c-gpio.h>
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = 1,
.scl_pin = 0,
.sda_pin = GPIO_PF1,
.scl_pin = GPIO_PF0,
.sda_is_open_drain = 0,
.scl_is_open_drain = 0,
.udelay = 40,
......@@ -420,6 +423,30 @@ static struct platform_device bfin_dpmc = {
},
};
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
/* TODO: add platform data here */
};
#endif
#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
/* TODO: add platform data here */
};
#endif
#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
static struct platform_device bfin_ac97 = {
.name = "bfin-ac97",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
/* TODO: add platform data here */
};
#endif
static struct platform_device *ezkit_devices[] __initdata = {
&bfin_dpmc,
......@@ -467,6 +494,18 @@ static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&ezkit_flash_device,
#endif
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
&bfin_tdm,
#endif
#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
&bfin_ac97,
#endif
};
static int __init ezkit_init(void)
......@@ -484,6 +523,17 @@ static int __init ezkit_init(void)
SSYNC();
#endif
#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
bfin_write_FIO0_FLAG_S(1 << 15);
SSYNC();
/*
* This initialization lasts for approximately 4500 MCLKs.
* MCLK = 12.288MHz
*/
udelay(400);
#endif
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
return 0;
}
......
arch/blackfin/mach-bf561/coreb.c
View file @ 7f388396
......@@ -18,9 +18,9 @@
#include <linux/miscdevice.h>
#include <linux/module.h>
#define CMD_COREB_START 2
#define CMD_COREB_STOP 3
#define CMD_COREB_RESET 4
#define CMD_COREB_START _IO('b', 0)
#define CMD_COREB_STOP _IO('b', 1)
#define CMD_COREB_RESET _IO('b', 2)
static long
coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
......@@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
switch (cmd) {
case CMD_COREB_START:
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
break;
case CMD_COREB_STOP:
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
break;
case CMD_COREB_RESET:
......@@ -74,3 +74,4 @@ module_exit(bf561_coreb_exit);
MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>");
MODULE_DESCRIPTION("BF561 Core B Support");
MODULE_LICENSE("GPL");
arch/blackfin/mach-bf561/include/mach/blackfin.h
View file @ 7f388396
......@@ -24,29 +24,16 @@
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
#define SIC_IWR0 SICA_IWR0
#define SIC_IWR1 SICA_IWR1
#define SIC_IAR0 SICA_IAR0
#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2))
#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2))
#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val)
/* Weird muxer funcs which pick SIC regs from IMASK base */
#define __SIC_MUX(base, x) ((base) + ((x) << 2))
#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
#define BFIN_UART_NR_PORTS 1
......
arch/blackfin/mach-bf561/include/mach/cdefBF561.h
View file @ 7f388396
......@@ -30,49 +30,41 @@
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define bfin_read_SWRST() bfin_read_SICA_SWRST()
#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val)
#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val)
#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val)
#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK)
#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val)
#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val)
#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val)
#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val)
#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val)
#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val)
#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val)
#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val)
#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val)
#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val)
#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val)
#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val)
#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val)
#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val)
#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val)
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
......
arch/blackfin/mach-bf561/include/mach/defBF561.h
View file @ 7f388396
......@@ -28,32 +28,29 @@
#define CHIPID 0xFFC00014 /* Chip ID Register */
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
#define RESET_SOFTWARE (SWRST_OCCURRED)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
#define SWRST 0xFFC00100 /* Software Reset register */
#define SYSCR 0xFFC00104 /* System Reset Configuration register */
#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
#define SICB_SWRST 0xFFC01100 /* reserved */
......@@ -1271,63 +1268,6 @@
#define PF14_P 14
#define PF15_P 15
/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
/* SPI_CTL Masks */
#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
/* SPI_FLG Masks */
#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPI_FLG Bit Positions */
#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
/* SPI_STAT Masks */
#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
/* AMGCTL Masks */
......
arch/blackfin/mach-bf561/ints-priority.c
View file @ 7f388396
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arch/blackfin/mach-bf561/smp.c
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arch/blackfin/mach-common/dpmc_modes.S
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arch/blackfin/mach-common/entry.S
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arch/blackfin/mach-common/interrupt.S
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arch/blackfin/mach-common/ints-priority.c
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arch/blackfin/mm/init.c
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......@@ -158,5 +158,8 @@ void __init_refok free_initmem(void)
free_init_pages("unused kernel memory",
(unsigned long)(&__init_begin),
(unsigned long)(&__init_end));
if (memory_start == (unsigned long)(&__init_end))
memory_start = (unsigned long)(&__init_begin);
#endif
}
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