[ARM] Fix a collection of missed changes from cache API changes.

arch/arm/kernel/signal.c

@@ -362,8 +362,8 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 		 * Ensure that the instruction cache sees
 		 * the return code written onto the stack.
 		 */
-		cpu_icache_invalidate_range((unsigned long)rc,
-					    (unsigned long)(rc + 1));
+		flush_icache_range((unsigned long)rc,
+				   (unsigned long)(rc + 1));
 
 		retcode = ((unsigned long)rc) + thumb;
 	}
@@ -570,6 +570,9 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
 				/* ldr	pc, [sp], #12 */
 				put_user(0xe49df00c, &usp[2]);
 
+				flush_icache_range((unsigned long)usp,
+						   (unsigned long)(usp + 3));
+
 				regs->ARM_pc = regs->ARM_sp + 4;
 			}
 		}

arch/arm/mach-sa1100/sleep.S

@@ -54,7 +54,7 @@ ENTRY(sa1100_cpu_suspend)
 	str	r0, [r1]
 
 	@ clean data cache and invalidate WB
-	bl	cpu_sa1100_cache_clean_invalidate_all
+	bl	v4wb_flush_kern_cache_all
 
 	@ disable clock switching
 	mcr	p15, 0, r1, c15, c2, 2

arch/arm/mm/proc-arm2_3.S

@@ -330,6 +330,7 @@ arm3_elf_name:	.asciz	"v2"
 		.long	arm2_processor_functions
 		.long	0
 		.long	0
+		.long	0
 
 		.long	0x41560250
 		.long	0xfffffff0
@@ -342,6 +343,7 @@ arm3_elf_name:	.asciz	"v2"
 		.long	arm250_processor_functions
 		.long	0
 		.long	0
+		.long	0
 
 		.long	0x41560300
 		.long	0xfffffff0
@@ -354,4 +356,5 @@ arm3_elf_name:	.asciz	"v2"
 		.long	arm3_processor_functions
 		.long	0
 		.long	0
+		.long	0
 

arch/arm/mm/proc-syms.c

@@ -11,27 +11,28 @@
 #include <linux/mm.h>
 
 #include <asm/cacheflush.h>
-#include <asm/pgalloc.h>
 #include <asm/proc-fns.h>
 #include <asm/tlbflush.h>
 
 EXPORT_SYMBOL(__flush_dcache_page);
 
 #ifndef MULTI_CPU
-EXPORT_SYMBOL(cpu_cache_clean_invalidate_all);
-EXPORT_SYMBOL(cpu_cache_clean_invalidate_range);
-EXPORT_SYMBOL(cpu_dcache_clean_page);
-EXPORT_SYMBOL(cpu_dcache_clean_entry);
-EXPORT_SYMBOL(cpu_dcache_clean_range);
-EXPORT_SYMBOL(cpu_dcache_invalidate_range);
-EXPORT_SYMBOL(cpu_icache_invalidate_range);
-EXPORT_SYMBOL(cpu_icache_invalidate_page);
-EXPORT_SYMBOL(cpu_set_pgd);
+EXPORT_SYMBOL(cpu_dcache_clean_area);
 EXPORT_SYMBOL(cpu_set_pte);
 #else
 EXPORT_SYMBOL(processor);
 #endif
 
+#ifndef MULTI_CACHE
+EXPORT_SYMBOL_NOVERS(__cpuc_flush_kern_all);
+EXPORT_SYMBOL_NOVERS(__cpuc_flush_user_all);
+EXPORT_SYMBOL_NOVERS(__cpuc_flush_user_range);
+EXPORT_SYMBOL_NOVERS(__cpuc_coherent_kern_range);
+EXPORT_SYMBOL_NOVERS(__cpuc_flush_dcache_page);
+#else
+EXPORT_SYMBOL(cpu_cache);
+#endif
+
 /*
  * No module should need to touch the TLB (and currently
  * no modules do.  We export this for "loadkernel" support