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Commit 81d6e59d authored by Linus Torvalds's avatar Linus Torvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (132 commits)
  sh: oprofile: Fix up the module build.
  sh: add UIO support for JPU on SH7722.
  serial: sh-sci: Fix up port pinmux for SH7366.
  sh: mach-rsk: Use uImage generation by default for rsk7201/7203.
  sh: mach-sh03: Fix up pata_platform build breakage.
  sh: enable deferred io LCDC on Migo-R
  video: sh_mobile_lcdcfb deferred io support
  video: deferred io with physically contiguous memory
  video: deferred io cleanup
  video: fix deferred io fsync()
  sh: add LCDC interrupt configuration to AP325 and Migo-R
  sh_mobile_lcdc: use FB_SYS helpers instead of FB_CFB
  sh: split coherent pages
  sh: dma: Kill off ISA DMA wrapper.
  sh: Conditionalize the code dumper on CONFIG_DUMP_CODE.
  sh: Kill off the unused SH_ALPHANUMERIC debug option.
  sh: Enable skipping of bss on debug platforms for sh32 also.
  doc: Update sh cpufreq documentation.
  sh: mrshpc_setup_windows() needs to be inline.
  serial: sh-sci: sci_poll_get_char() is only used by CONFIG_CONSOLE_POLL.
  ...
parents 4a6908a3 59de580a
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Documentation/cpu-freq/user-guide.txt
View file @ 81d6e59d
......@@ -93,10 +93,8 @@ Several "PowerBook" and "iBook2" notebooks are supported.
1.5 SuperH
----------
The following SuperH processors are supported by cpufreq:
SH-3
SH-4
All SuperH processors supporting rate rounding through the clock
framework are supported by cpufreq.
1.6 Blackfin
------------
......
Documentation/sh/kgdb.txt deleted 100644 → 0
View file @ 4a6908a3
This file describes the configuration and behavior of KGDB for the SH
kernel. Based on a description from Henry Bell <henry.bell@st.com>, it
has been modified to account for quirks in the current implementation.
Version
=======
This version of KGDB was written for 2.4.xx kernels for the SH architecture.
Further documentation is available from the linux-sh project website.
Debugging Setup: Host
======================
The two machines will be connected together via a serial line - this
should be a null modem cable i.e. with a twist.
On your DEVELOPMENT machine, go to your kernel source directory and
build the kernel, enabling KGDB support in the "kernel hacking" section.
This includes the KGDB code, and also makes the kernel be compiled with
the "-g" option set -- necessary for debugging.
To install this new kernel, use the following installation procedure.
Decide on which tty port you want the machines to communicate, then
cable them up back-to-back using the null modem. On the DEVELOPMENT
machine, you may wish to create an initialization file called .gdbinit
(in the kernel source directory or in your home directory) to execute
commonly-used commands at startup.
A minimal .gdbinit might look like this:
file vmlinux
set remotebaud 115200
target remote /dev/ttyS0
Change the "target" definition so that it specifies the tty port that
you intend to use. Change the "remotebaud" definition to match the
data rate that you are going to use for the com line (115200 is the
default).
Debugging Setup: Target
========================
By default, the KGDB stub will communicate with the host GDB using
ttySC1 at 115200 baud, 8 databits, no parity; these defaults can be
changed in the kernel configuration. As the kernel starts up, KGDB will
initialize so that breakpoints, kernel segfaults, and so forth will
generally enter the debugger.
This behavior can be modified by including the "kgdb" option in the
kernel command line; this option has the general form:
kgdb=<ttyspec>,<action>
The <ttyspec> indicates the port to use, and can optionally specify
baud, parity and databits -- e.g. "ttySC0,9600N8" or "ttySC1,19200".
The <action> can be "halt" or "disabled". The "halt" action enters the
debugger via a breakpoint as soon as kgdb is initialized; the "disabled"
action causes kgdb to ignore kernel segfaults and such until explicitly
entered by a breakpoint in the code or by external action (sysrq or NMI).
(Both <ttyspec> and <action> can appear alone, w/o the separating comma.)
For example, if you wish to debug early in kernel startup code, you
might specify the halt option:
kgdb=halt
Boot the TARGET machine, which will appear to hang.
On your DEVELOPMENT machine, cd to the source directory and run the gdb
program. (This is likely to be a cross GDB which runs on your host but
is built for an SH target.) If everything is working correctly you
should see gdb print out a few lines indicating that a breakpoint has
been taken. It will actually show a line of code in the target kernel
inside the gdbstub activation code.
NOTE: BE SURE TO TERMINATE OR SUSPEND any other host application which
may be using the same serial port (for example, a terminal emulator you
have been using to connect to the target boot code.) Otherwise, data
from the target may not all get to GDB!
You can now use whatever gdb commands you like to set breakpoints.
Enter "continue" to start your target machine executing again. At this
point the target system will run at full speed until it encounters
your breakpoint or gets a segment violation in the kernel, or whatever.
Serial Ports: KGDB, Console
============================
This version of KGDB may not gracefully handle conflict with other
drivers in the kernel using the same port. If KGDB is configured on the
same port (and with the same parameters) as the kernel console, or if
CONFIG_SH_KGDB_CONSOLE is configured, things should be fine (though in
some cases console messages may appear twice through GDB). But if the
KGDB port is not the kernel console and used by another serial driver
which assumes different serial parameters (e.g. baud rate) KGDB may not
recover.
Also, when KGDB is entered via sysrq-g (requires CONFIG_KGDB_SYSRQ) and
the kgdb port uses the same port as the console, detaching GDB will not
restore the console to working order without the port being re-opened.
Another serious consequence of this is that GDB currently CANNOT break
into KGDB externally (e.g. via ^C or <BREAK>); unless a breakpoint or
error is encountered, the only way to enter KGDB after the initial halt
(see above) is via NMI (CONFIG_KGDB_NMI) or sysrq-g (CONFIG_KGDB_SYSRQ).
Code is included for the basic Hitachi Solution Engine boards to allow
the use of ttyS0 for KGDB if desired; this is less robust, but may be
useful in some cases. (This cannot be selected using the config file,
but only through the kernel command line, e.g. "kgdb=ttyS0", though the
configured defaults for baud rate etc. still apply if not overridden.)
If gdbstub Does Not Work
========================
If it doesn't work, you will have to troubleshoot it. Do the easy
things first like double checking your cabling and data rates. You
might try some non-kernel based programs to see if the back-to-back
connection works properly. Just something simple like cat /etc/hosts
/dev/ttyS0 on one machine and cat /dev/ttyS0 on the other will tell you
if you can send data from one machine to the other. There is no point
in tearing out your hair in the kernel if the line doesn't work.
If you need to debug the GDB/KGDB communication itself, the gdb commands
"set debug remote 1" and "set debug serial 1" may be useful, but be
warned: they produce a lot of output.
Threads
=======
Each process in a target machine is seen as a gdb thread. gdb thread related
commands (info threads, thread n) can be used. CONFIG_KGDB_THREAD must
be defined for this to work.
In this version, kgdb reports PID_MAX (32768) as the process ID for the
idle process (pid 0), since GDB does not accept 0 as an ID.
Detaching (exiting KGDB)
=========================
There are two ways to resume full-speed target execution: "continue" and
"detach". With "continue", GDB inserts any specified breakpoints in the
target code and resumes execution; the target is still in "gdb mode".
If a breakpoint or other debug event (e.g. NMI) happens, the target
halts and communicates with GDB again, which is waiting for it.
With "detach", GDB does *not* insert any breakpoints; target execution
is resumed and GDB stops communicating (does not wait for the target).
In this case, the target is no longer in "gdb mode" -- for example,
console messages no longer get sent separately to the KGDB port, or
encapsulated for GDB. If a debug event (e.g. NMI) occurs, the target
will re-enter "gdb mode" and will display this fact on the console; you
must give a new "target remote" command to gdb.
NOTE: TO AVOID LOSSING CONSOLE MESSAGES IN CASE THE KERNEL CONSOLE AND
KGDB USING THE SAME PORT, THE TARGET WAITS FOR ANY INPUT CHARACTER ON
THE KGDB PORT AFTER A DETACH COMMAND. For example, after the detach you
could start a terminal emulator on the same host port and enter a <cr>;
however, this program must then be terminated or suspended in order to
use GBD again if KGDB is re-entered.
Acknowledgements
================
This code was mostly generated by Henry Bell <henry.bell@st.com>;
largely from KGDB by Amit S. Kale <akale@veritas.com> - extracts from
code by Glenn Engel, Jim Kingdon, David Grothe <dave@gcom.com>, Tigran
Aivazian <tigran@sco.com>, William Gatliff <bgat@open-widgets.com>, Ben
Lee, Steve Chamberlain and Benoit Miller <fulg@iname.com> are also
included.
Jeremy Siegel
<jsiegel@mvista.com>
arch/sh/Kconfig
View file @ 81d6e59d
......@@ -13,6 +13,7 @@ config SUPERH
select HAVE_OPROFILE
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IOREMAP_PROT if MMU
select HAVE_ARCH_TRACEHOOK
help
The SuperH is a RISC processor targeted for use in embedded systems
and consumer electronics; it was also used in the Sega Dreamcast
......@@ -23,8 +24,10 @@ config SUPERH32
def_bool !SUPERH64
select HAVE_KPROBES
select HAVE_KRETPROBES
select HAVE_ARCH_TRACEHOOK
select HAVE_FUNCTION_TRACER
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_DYNAMIC_FTRACE
select HAVE_ARCH_KGDB
config SUPERH64
def_bool y if CPU_SH5
......@@ -55,8 +58,6 @@ config GENERIC_HARDIRQS
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
depends on SUPERH32 && (!SH_DREAMCAST && !SH_SH4202_MICRODEV && \
!SH_7751_SYSTEMH && !HD64461)
config GENERIC_IRQ_PROBE
def_bool y
......@@ -85,10 +86,17 @@ config GENERIC_LOCKBREAK
config SYS_SUPPORTS_PM
bool
depends on !SMP
config ARCH_SUSPEND_POSSIBLE
def_bool n
config ARCH_HIBERNATION_POSSIBLE
def_bool n
config SYS_SUPPORTS_APM_EMULATION
bool
select SYS_SUPPORTS_PM
select ARCH_SUSPEND_POSSIBLE
config SYS_SUPPORTS_SMP
bool
......@@ -183,6 +191,11 @@ config CPU_SUBTYPE_SH7619
# SH-2A Processor Support
config CPU_SUBTYPE_SH7201
bool "Support SH7201 processor"
select CPU_SH2A
select CPU_HAS_FPU
config CPU_SUBTYPE_SH7203
bool "Support SH7203 processor"
select CPU_SH2A
......@@ -456,8 +469,12 @@ config SH_CPU_FREQ
depends on CPU_FREQ
select CPU_FREQ_TABLE
help
This adds the cpufreq driver for SuperH. At present, only
the SH-4 is supported.
This adds the cpufreq driver for SuperH. Any CPU that supports
clock rate rounding through the clock framework can use this
driver. While it will make the kernel slightly larger, this is
harmless for CPUs that don't support rate rounding. The driver
will also generate a notice in the boot log before disabling
itself if the CPU in question is not capable of rate rounding.
For details, take a look at <file:Documentation/cpu-freq>.
......@@ -469,9 +486,6 @@ source "arch/sh/drivers/Kconfig"
endmenu
config ISA_DMA_API
bool
menu "Kernel features"
source kernel/Kconfig.hz
......@@ -688,49 +702,6 @@ config MAPLE
Dreamcast with a serial line terminal or a remote network
connection.
config CF_ENABLER
bool "Compact Flash Enabler support"
depends on SOLUTION_ENGINE || SH_SH03
---help---
Compact Flash is a small, removable mass storage device introduced
in 1994 originally as a PCMCIA device. If you say `Y' here, you
compile in support for Compact Flash devices directly connected to
a SuperH processor. A Compact Flash FAQ is available at
<http://www.compactflash.org/faqs/faq.htm>.
If your board has "Directly Connected" CompactFlash at area 5 or 6,
you may want to enable this option. Then, you can use CF as
primary IDE drive (only tested for SanDisk).
If in doubt, select 'N'.
choice
prompt "Compact Flash Connection Area"
depends on CF_ENABLER
default CF_AREA6
config CF_AREA5
bool "Area5"
help
If your board has "Directly Connected" CompactFlash, You should
select the area where your CF is connected to.
- "Area5" if CompactFlash is connected to Area 5 (0x14000000)
- "Area6" if it is connected to Area 6 (0x18000000)
"Area6" will work for most boards.
config CF_AREA6
bool "Area6"
endchoice
config CF_BASE_ADDR
hex
depends on CF_ENABLER
default "0xb8000000" if CF_AREA6
default "0xb4000000" if CF_AREA5
source "arch/sh/drivers/pci/Kconfig"
source "drivers/pci/Kconfig"
......@@ -748,13 +719,11 @@ source "fs/Kconfig.binfmt"
endmenu
menu "Power management options (EXPERIMENTAL)"
depends on EXPERIMENTAL && SYS_SUPPORTS_PM
depends on EXPERIMENTAL
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on !SMP
source "kernel/power/Kconfig"
source kernel/power/Kconfig
source "drivers/cpuidle/Kconfig"
endmenu
......
arch/sh/Kconfig.debug
View file @ 81d6e59d
......@@ -98,18 +98,29 @@ config IRQSTACKS
for handling hard and soft interrupts. This can help avoid
overflowing the process kernel stacks.
config SH_KGDB
bool "Include KGDB kernel debugger"
select FRAME_POINTER
select DEBUG_INFO
depends on CPU_SH3 || CPU_SH4
config DUMP_CODE
bool "Show disassembly of nearby code in register dumps"
depends on DEBUG_KERNEL && SUPERH32
default y if DEBUG_BUGVERBOSE
default n
help
This prints out a code trace of the instructions leading up to
the faulting instruction as a debugging aid. As this does grow
the kernel in size a bit, most users will want to say N here.
Those looking for more verbose debugging output should say Y.
config SH_NO_BSS_INIT
bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)"
depends on DEBUG_KERNEL
default n
help
Include in-kernel hooks for kgdb, the Linux kernel source level
debugger. See <http://kgdb.sourceforge.net/> for more information.
Unless you are intending to debug the kernel, say N here.
If running in painfully slow environments, such as an RTL
simulation or from remote memory via SHdebug, where the memory
can already be gauranteed to ber zeroed on boot, say Y.
menu "KGDB configuration options"
depends on SH_KGDB
For all other cases, say N. If this option seems perplexing, or
you aren't sure, say N.
config MORE_COMPILE_OPTIONS
bool "Add any additional compile options"
......@@ -122,85 +133,16 @@ config COMPILE_OPTIONS
string "Additional compile arguments"
depends on MORE_COMPILE_OPTIONS
config KGDB_NMI
def_bool n
prompt "Enter KGDB on NMI"
config SH_KGDB_CONSOLE
def_bool n
prompt "Console messages through GDB"
depends on !SERIAL_SH_SCI_CONSOLE && SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
config KGDB_SYSRQ
def_bool y
prompt "Allow SysRq 'G' to enter KGDB"
depends on MAGIC_SYSRQ
comment "Serial port setup"
config KGDB_DEFPORT
int "Port number (ttySCn)"
default "1"
config KGDB_DEFBAUD
int "Baud rate"
default "115200"
choice
prompt "Parity"
depends on SH_KGDB
default KGDB_DEFPARITY_N
config KGDB_DEFPARITY_N
bool "None"
config KGDB_DEFPARITY_E
bool "Even"
config KGDB_DEFPARITY_O
bool "Odd"
endchoice
choice
prompt "Data bits"
depends on SH_KGDB
default KGDB_DEFBITS_8
config KGDB_DEFBITS_8
bool "8"
config KGDB_DEFBITS_7
bool "7"
endchoice
endmenu
if SUPERH64
config SH64_PROC_ASIDS
bool "Debug: report ASIDs through /proc/asids"
depends on PROC_FS && MMU
config SH64_SR_WATCH
bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
depends on SUPERH64
config POOR_MANS_STRACE
bool "Debug: enable rudimentary strace facility"
depends on SUPERH64
help
This option allows system calls to be traced to the console. It also
aids in detecting kernel stack underflow. It is useful for debugging
early-userland problems (e.g. init incurring fatal exceptions.)
config SH_ALPHANUMERIC
bool "Enable debug outputs to on-board alphanumeric display"
depends on SH_CAYMAN
config SH_NO_BSS_INIT
bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)"
endif
endmenu
arch/sh/Makefile
View file @ 81d6e59d
......@@ -32,6 +32,7 @@ cflags-$(CONFIG_CPU_SH4) := $(call cc-option,-m4,) \
$(call cc-option,-mno-implicit-fp,-m4-nofpu)
cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
$(call cc-option,-m4a-nofpu,)
cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,)
cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,)
ifeq ($(cflags-y),)
......@@ -39,22 +40,16 @@ ifeq ($(cflags-y),)
# In the case where we are stuck with a compiler that has been uselessly
# restricted to a particular ISA, a favourite default of newer GCCs when
# extensive multilib targets are not provided, ensure we get the best fit
# regarding FP generation. This is necessary to avoid references to FP
# variants in libgcc where integer variants exist, which otherwise result
# in link errors. This is intentionally stupid (albeit many orders of
# magnitude less than GCC's default behaviour), as anything with a large
# number of multilib targets better have been built correctly for
# the target in mind.
# regarding FP generation. This is intentionally stupid (albeit many
# orders of magnitude less than GCC's default behaviour), as anything
# with a large number of multilib targets better have been built
# correctly for the target in mind.
#
cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \
grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//')
endif
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
cflags-y += $(call cc-option,-mno-fdpic)
# At this point, anything goes.
isaflags-y := $(call as-option,-Wa$(comma)-isa=any,)
else
#
# -Wa,-isa= tuning implies -Wa,-dsp for the versions of binutils that
# support it, while -Wa,-dsp by itself limits the range of usable opcodes
......@@ -67,7 +62,12 @@ isaflags-y := $(call as-option,-Wa$(comma)-isa=$(isa-y),)
isaflags-$(CONFIG_SH_DSP) := \
$(call as-option,-Wa$(comma)-isa=$(isa-y),-Wa$(comma)-dsp)
endif
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
cflags-y += $(call cc-option,-mno-fdpic)
cflags-y += $(isaflags-y) -ffreestanding
cflags-$(CONFIG_MORE_COMPILE_OPTIONS) += \
......@@ -79,6 +79,9 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
# Give the various platforms the opportunity to set default image types
defaultimage-$(CONFIG_SUPERH32) := zImage
defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
defaultimage-$(CONFIG_SH_RSK) := uImage
defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
# Set some sensible Kbuild defaults
KBUILD_DEFCONFIG := shx3_defconfig
......@@ -132,6 +135,7 @@ machdir-$(CONFIG_SH_LANDISK) += mach-landisk
machdir-$(CONFIG_SH_TITAN) += mach-titan
machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2
machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
machdir-$(CONFIG_SH_RSK) += mach-rsk
ifneq ($(machdir-y),)
core-y += $(addprefix arch/sh/boards/, \
......@@ -173,11 +177,8 @@ KBUILD_CFLAGS += -pipe $(cflags-y)
KBUILD_CPPFLAGS += $(cflags-y)
KBUILD_AFLAGS += $(cflags-y)
LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
libs-y += $(LIBGCC)
PHONY += maketools FORCE
......
arch/sh/boards/Kconfig
View file @ 81d6e59d
......@@ -126,10 +126,12 @@ config SH_RTS7751R2D
Select RTS7751R2D if configuring for a Renesas Technology
Sales SH-Graphics board.
config SH_RSK7203
bool "RSK7203"
select GENERIC_GPIO
depends on CPU_SUBTYPE_SH7203
config SH_RSK
bool "Renesas Starter Kit"
depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203
help
Select this option if configuring for any of the RSK+ MCU
evaluation platforms.
config SH_SDK7780
bool "SDK7780R3"
......@@ -253,6 +255,7 @@ source "arch/sh/boards/mach-r2d/Kconfig"
source "arch/sh/boards/mach-highlander/Kconfig"
source "arch/sh/boards/mach-sdk7780/Kconfig"
source "arch/sh/boards/mach-migor/Kconfig"
source "arch/sh/boards/mach-rsk/Kconfig"
if SH_MAGIC_PANEL_R2
......
arch/sh/boards/Makefile
View file @ 81d6e59d
......@@ -3,7 +3,6 @@
#
obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o
obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
obj-$(CONFIG_SH_RSK7203) += board-rsk7203.o
obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
obj-$(CONFIG_SH_SHMIN) += board-shmin.o
obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
arch/sh/boards/board-ap325rxa.c
View file @ 81d6e59d
......@@ -197,6 +197,10 @@ static struct resource lcdc_resources[] = {
.end = 0xfe941fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 28,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
......@@ -303,6 +307,7 @@ static struct resource ceu_resources[] = {
static struct platform_device ceu_device = {
.name = "sh_mobile_ceu",
.id = 0, /* "ceu0" clock */
.num_resources = ARRAY_SIZE(ceu_resources),
.resource = ceu_resources,
.dev = {
......@@ -344,7 +349,6 @@ static int __init ap325rxa_devices_setup(void)
gpio_export(GPIO_PTF7, 0);
/* LCDC */
clk_always_enable("mstp200");
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
......@@ -375,7 +379,6 @@ static int __init ap325rxa_devices_setup(void)
gpio_direction_output(GPIO_PTS3, 1);
/* CEU */
clk_always_enable("mstp203");
gpio_request(GPIO_FN_VIO_CLK2, NULL);
gpio_request(GPIO_FN_VIO_VD2, NULL);
gpio_request(GPIO_FN_VIO_HD2, NULL);
......
arch/sh/boards/board-shmin.c
View file @ 81d6e59d
......@@ -22,21 +22,13 @@ static void __init init_shmin_irq(void)
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size)
static void __init shmin_setup(char **cmdline_p)
{
static int dummy;
if ((port & ~0x1f) == SHMIN_NE_BASE)
return (void __iomem *)(SHMIN_IO_BASE + port);
dummy = 0;
return &dummy;
__set_io_port_base(SHMIN_IO_BASE);
}
static struct sh_machine_vector mv_shmin __initmv = {
.mv_name = "SHMIN",
.mv_setup = shmin_setup,
.mv_init_irq = init_shmin_irq,
.mv_ioport_map = shmin_ioport_map,
};
arch/sh/boards/mach-cayman/Makefile
View file @ 81d6e59d
......@@ -2,4 +2,3 @@
# Makefile for the Hitachi Cayman specific parts of the kernel
#
obj-y := setup.o irq.o
obj-$(CONFIG_HEARTBEAT) += led.o
arch/sh/boards/mach-cayman/irq.c
View file @ 81d6e59d
......@@ -94,31 +94,11 @@ static void ack_cayman_irq(unsigned int irq)
disable_cayman_irq(irq);
}
static void end_cayman_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_cayman_irq(irq);
}
static unsigned int startup_cayman_irq(unsigned int irq)
{
enable_cayman_irq(irq);
return 0; /* never anything pending */
}
static void shutdown_cayman_irq(unsigned int irq)
{
disable_cayman_irq(irq);
}
struct hw_interrupt_type cayman_irq_type = {
.typename = "Cayman-IRQ",
.startup = startup_cayman_irq,
.shutdown = shutdown_cayman_irq,
.enable = enable_cayman_irq,
.disable = disable_cayman_irq,
.ack = ack_cayman_irq,
.end = end_cayman_irq,
struct irq_chip cayman_irq_type = {
.name = "Cayman-IRQ",
.unmask = enable_cayman_irq,
.mask = disable_cayman_irq,
.mask_ack = ack_cayman_irq,
};
int cayman_irq_demux(int evt)
......@@ -187,8 +167,9 @@ void init_cayman_irq(void)
return;
}
for (i=0; i<NR_EXT_IRQS; i++) {
irq_desc[START_EXT_IRQS + i].chip = &cayman_irq_type;
for (i = 0; i < NR_EXT_IRQS; i++) {
set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type,
handle_level_irq);
}
/* Setup the SMSC interrupt */
......
arch/sh/boards/mach-cayman/led.c deleted 100644 → 0
View file @ 4a6908a3
/*
* arch/sh/boards/cayman/led.c
*
* Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Flash the LEDs
*/
#include <asm/io.h>
/*
** It is supposed these functions to be used for a low level
** debugging (via Cayman LEDs), hence to be available as soon
** as possible.
** Unfortunately Cayman LEDs relies on Cayman EPLD to be mapped
** (this happen when IRQ are initialized... quite late).
** These triky dependencies should be removed. Temporary, it
** may be enough to NOP until EPLD is mapped.
*/
extern unsigned long epld_virt;
#define LED_ADDR (epld_virt + 0x008)
#define HDSP2534_ADDR (epld_virt + 0x100)
void mach_led(int position, int value)
{
if (!epld_virt)
return;
if (value)
ctrl_outl(0, LED_ADDR);
else
ctrl_outl(1, LED_ADDR);
}
void mach_alphanum(int position, unsigned char value)
{
if (!epld_virt)
return;
ctrl_outb(value, HDSP2534_ADDR + 0xe0 + (position << 2));
}
void mach_alphanum_brightness(int setting)
{
ctrl_outb(setting & 7, HDSP2534_ADDR + 0xc0);
}
arch/sh/boards/mach-dreamcast/irq.c
View file @ 81d6e59d
......@@ -10,106 +10,90 @@
*/
#include <linux/irq.h>
#include <asm/io.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <mach/sysasic.h>
/* Dreamcast System ASIC Hardware Events -
The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
hardware events from system peripherals and triggering an SH7750 IRQ.
Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
set in the Event Mask Registers (EMRs). When a hardware event is
triggered, it's corresponding bit in the Event Status Registers (ESRs)
is set, and that bit should be rewritten to the ESR to acknowledge that
event.
There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
groups of EMRs that parallel the ESRs. Each EMR group corresponds to an
IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
In the kernel, these events are mapped to virtual IRQs so that drivers can
respond to them as they would a normal interrupt. In order to keep this
mapping simple, the events are mapped as:
6900/6910 - Events 0-31, IRQ 13
6904/6924 - Events 32-63, IRQ 11
6908/6938 - Events 64-95, IRQ 9
*/
/*
* Dreamcast System ASIC Hardware Events -
*
* The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
* hardware events from system peripherals and triggering an SH7750 IRQ.
* Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
* set in the Event Mask Registers (EMRs). When a hardware event is
* triggered, its corresponding bit in the Event Status Registers (ESRs)
* is set, and that bit should be rewritten to the ESR to acknowledge that
* event.
*
* There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
* types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
* There are three groups of EMRs that parallel the ESRs. Each EMR group
* corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
* 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
* triggers IRQ 9.
*
* In the kernel, these events are mapped to virtual IRQs so that drivers can
* respond to them as they would a normal interrupt. In order to keep this
* mapping simple, the events are mapped as:
*
* 6900/6910 - Events 0-31, IRQ 13
* 6904/6924 - Events 32-63, IRQ 11
* 6908/6938 - Events 64-95, IRQ 9
*
*/
#define ESR_BASE 0x005f6900 /* Base event status register */
#define EMR_BASE 0x005f6910 /* Base event mask register */
/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
1 = 0x6920, 2 = 0x6930; also determine the event offset */
/*
* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
* 1 = 0x6920, 2 = 0x6930; also determine the event offset.
*/
#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
/* Return the hardware event's bit positon within the EMR/ESR */
#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
(logically mapped to the corresponding bit for the hardware event). */
/*
* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
* (logically mapped to the corresponding bit for the hardware event).
*/
/* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(unsigned int irq)
{
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
mask = inl(emr);
mask &= ~(1 << EVENT_BIT(irq));
outl(mask, emr);
mask = inl(emr);
mask &= ~(1 << EVENT_BIT(irq));
outl(mask, emr);
}
/* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(unsigned int irq)
{
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
__u32 mask;
mask = inl(emr);
mask |= (1 << EVENT_BIT(irq));
outl(mask, emr);
mask = inl(emr);
mask |= (1 << EVENT_BIT(irq));
outl(mask, emr);
}
/* Acknowledge a hardware event by writing its bit back to its ESR */
static void ack_systemasic_irq(unsigned int irq)
{
__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
disable_systemasic_irq(irq);
outl((1 << EVENT_BIT(irq)), esr);
}
/* After a IRQ has been ack'd and responded to, it needs to be renabled */
static void end_systemasic_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_systemasic_irq(irq);
}
static unsigned int startup_systemasic_irq(unsigned int irq)
{
enable_systemasic_irq(irq);
return 0;
}
static void shutdown_systemasic_irq(unsigned int irq)
static void mask_ack_systemasic_irq(unsigned int irq)
{
disable_systemasic_irq(irq);
__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
disable_systemasic_irq(irq);
outl((1 << EVENT_BIT(irq)), esr);
}
struct hw_interrupt_type systemasic_int = {
.typename = "System ASIC",
.startup = startup_systemasic_irq,
.shutdown = shutdown_systemasic_irq,
.enable = enable_systemasic_irq,
.disable = disable_systemasic_irq,
.ack = ack_systemasic_irq,
.end = end_systemasic_irq,
struct irq_chip systemasic_int = {
.name = "System ASIC",
.mask = disable_systemasic_irq,
.mask_ack = mask_ack_systemasic_irq,
.unmask = enable_systemasic_irq,
};
/*
......@@ -117,37 +101,37 @@ struct hw_interrupt_type systemasic_int = {
*/
int systemasic_irq_demux(int irq)
{
__u32 emr, esr, status, level;
__u32 j, bit;
switch (irq) {
case 13:
level = 0;
break;
case 11:
level = 1;
break;
case 9:
level = 2;
break;
default:
return irq;
}
emr = EMR_BASE + (level << 4) + (level << 2);
esr = ESR_BASE + (level << 2);
/* Mask the ESR to filter any spurious, unwanted interrupts */
status = inl(esr);
status &= inl(emr);
/* Now scan and find the first set bit as the event to map */
for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
if (status & bit) {
irq = HW_EVENT_IRQ_BASE + j + (level << 5);
return irq;
}
}
/* Not reached */
return irq;
__u32 emr, esr, status, level;
__u32 j, bit;
switch (irq) {
case 13:
level = 0;
break;
case 11:
level = 1;
break;
case 9:
level = 2;
break;
default:
return irq;
}
emr = EMR_BASE + (level << 4) + (level << 2);
esr = ESR_BASE + (level << 2);
/* Mask the ESR to filter any spurious, unwanted interrupts */
status = inl(esr);
status &= inl(emr);
/* Now scan and find the first set bit as the event to map */
for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
if (status & bit) {
irq = HW_EVENT_IRQ_BASE + j + (level << 5);
return irq;
}
}
/* Not reached */
return irq;
}
arch/sh/boards/mach-dreamcast/setup.c
View file @ 81d6e59d
......@@ -28,7 +28,7 @@
#include <asm/machvec.h>
#include <mach/sysasic.h>
extern struct hw_interrupt_type systemasic_int;
extern struct irq_chip systemasic_int;
extern void aica_time_init(void);
extern int gapspci_init(void);
extern int systemasic_irq_demux(int);
......@@ -47,7 +47,8 @@ static void __init dreamcast_setup(char **cmdline_p)
/* Assign all virtual IRQs to the System ASIC int. handler */
for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
irq_desc[i].chip = &systemasic_int;
set_irq_chip_and_handler(i, &systemasic_int,
handle_level_irq);
board_time_init = aica_time_init;
......
arch/sh/boards/mach-edosk7705/Makefile
View file @ 81d6e59d
......@@ -3,4 +3,3 @@
#
obj-y := setup.o io.o
arch/sh/boards/mach-edosk7705/io.c
View file @ 81d6e59d
......@@ -10,28 +10,24 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
#include <linux/io.h>
#include <mach/edosk7705.h>
#include <asm/addrspace.h>
#define SMC_IOADDR 0xA2000000
#define maybebadio(name,port) \
printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \
#name, (port), (__u32) __builtin_return_address(0))
/* Map the Ethernet addresses as if it is at 0x300 - 0x320 */
unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
static unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
{
if (port >= 0x300 && port < 0x320) {
/* SMC91C96 registers are 4 byte aligned rather than the
* usual 2 byte!
*/
return SMC_IOADDR + ( (port - 0x300) * 2);
}
/*
* SMC91C96 registers are 4 byte aligned rather than the
* usual 2 byte!
*/
if (port >= 0x300 && port < 0x320)
return SMC_IOADDR + ((port - 0x300) * 2);
maybebadio(sh_edosk7705_isa_port2addr, port);
return port;
maybebadio(port);
return port;
}
/* Trying to read / write bytes on odd-byte boundaries to the Ethernet
......@@ -42,53 +38,34 @@ unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
*/
unsigned char sh_edosk7705_inb(unsigned long port)
{
if (port >= 0x300 && port < 0x320 && port & 0x01) {
return (volatile unsigned char)(generic_inw(port -1) >> 8);
}
return *(volatile unsigned char *)sh_edosk7705_isa_port2addr(port);
}
if (port >= 0x300 && port < 0x320 && port & 0x01)
return __raw_readw(port - 1) >> 8;
unsigned int sh_edosk7705_inl(unsigned long port)
{
return *(volatile unsigned long *)port;
return __raw_readb(sh_edosk7705_isa_port2addr(port));
}
void sh_edosk7705_outb(unsigned char value, unsigned long port)
{
if (port >= 0x300 && port < 0x320 && port & 0x01) {
generic_outw(((unsigned short)value << 8), port -1);
__raw_writew(((unsigned short)value << 8), port - 1);
return;
}
*(volatile unsigned char *)sh_edosk7705_isa_port2addr(port) = value;
}
void sh_edosk7705_outl(unsigned int value, unsigned long port)
{
*(volatile unsigned long *)port = value;
__raw_writeb(value, sh_edosk7705_isa_port2addr(port));
}
void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count)
{
unsigned char *p = addr;
while (count--) *p++ = sh_edosk7705_inb(port);
}
void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count)
{
unsigned long *p = (unsigned long*)addr;
while (count--)
*p++ = *(volatile unsigned long *)port;
*p++ = sh_edosk7705_inb(port);
}
void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count)
{
unsigned char *p = (unsigned char*)addr;
while (count--) sh_edosk7705_outb(*p++, port);
}
unsigned char *p = (unsigned char *)addr;
void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count)
{
unsigned long *p = (unsigned long*)addr;
while (count--) sh_edosk7705_outl(*p++, port);
while (count--)
sh_edosk7705_outb(*p++, port);
}
arch/sh/boards/mach-edosk7705/setup.c
View file @ 81d6e59d
......@@ -9,6 +9,7 @@
* board by S. Dunn, 2003.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/machvec.h>
#include <mach/edosk7705.h>
......@@ -26,18 +27,10 @@ static struct sh_machine_vector mv_edosk7705 __initmv = {
.mv_nr_irqs = 80,
.mv_inb = sh_edosk7705_inb,
.mv_inl = sh_edosk7705_inl,
.mv_outb = sh_edosk7705_outb,
.mv_outl = sh_edosk7705_outl,
.mv_inl_p = sh_edosk7705_inl,
.mv_outl_p = sh_edosk7705_outl,
.mv_insb = sh_edosk7705_insb,
.mv_insl = sh_edosk7705_insl,
.mv_outsb = sh_edosk7705_outsb,
.mv_outsl = sh_edosk7705_outsl,
.mv_isa_port2addr = sh_edosk7705_isa_port2addr,
.mv_init_irq = sh_edosk7705_init_irq,
};
arch/sh/boards/mach-hp6xx/pm.c
View file @ 81d6e59d
......@@ -10,15 +10,91 @@
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <asm/io.h>
#include <asm/hd64461.h>
#include <mach/hp6xx.h>
#include <cpu/dac.h>
#include <asm/pm.h>
#include <asm/freq.h>
#include <asm/watchdog.h>
#define INTR_OFFSET 0x600
#define STBCR 0xffffff82
#define STBCR2 0xffffff88
#define STBCR_STBY 0x80
#define STBCR_MSTP2 0x04
#define MCR 0xffffff68
#define RTCNT 0xffffff70
#define MCR_RMODE 2
#define MCR_RFSH 4
extern u8 wakeup_start;
extern u8 wakeup_end;
static void pm_enter(void)
{
u8 stbcr, csr;
u16 frqcr, mcr;
u32 vbr_new, vbr_old;
set_bl_bit();
/* set wdt */
csr = sh_wdt_read_csr();
csr &= ~WTCSR_TME;
csr |= WTCSR_CKS_4096;
sh_wdt_write_csr(csr);
csr = sh_wdt_read_csr();
sh_wdt_write_cnt(0);
/* disable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
ctrl_outw(frqcr, FRQCR);
/* enable standby */
stbcr = ctrl_inb(STBCR);
ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
/* set self-refresh */
mcr = ctrl_inw(MCR);
ctrl_outw(mcr & ~MCR_RFSH, MCR);
/* set interrupt handler */
asm volatile("stc vbr, %0" : "=r" (vbr_old));
vbr_new = get_zeroed_page(GFP_ATOMIC);
udelay(50);
memcpy((void*)(vbr_new + INTR_OFFSET),
&wakeup_start, &wakeup_end - &wakeup_start);
asm volatile("ldc %0, vbr" : : "r" (vbr_new));
ctrl_outw(0, RTCNT);
ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR);
cpu_sleep();
asm volatile("ldc %0, vbr" : : "r" (vbr_old));
free_page(vbr_new);
/* enable PLL1 */
frqcr = ctrl_inw(FRQCR);
frqcr |= FRQCR_PSTBY;
ctrl_outw(frqcr, FRQCR);
udelay(50);
frqcr |= FRQCR_PLLEN;
ctrl_outw(frqcr, FRQCR);
ctrl_outb(stbcr, STBCR);
clear_bl_bit();
}
static int hp6x0_pm_enter(suspend_state_t state)
{
u8 stbcr, stbcr2;
......
arch/sh/boards/mach-microdev/Makefile
View file @ 81d6e59d
......@@ -2,7 +2,4 @@
# Makefile for the SuperH MicroDev specific parts of the kernel
#
obj-y := setup.o irq.o io.o
obj-$(CONFIG_HEARTBEAT) += led.o
obj-y := setup.o irq.o io.o fdc37c93xapm.o
arch/sh/boards/mach-microdev/fdc37c93xapm.c 0 → 100644
View file @ 81d6e59d
/*
*
* Setup for the SMSC FDC37C93xAPM
*
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
* Copyright (C) 2003, 2004 SuperH, Inc.
* Copyright (C) 2004, 2005 Paul Mundt
*
* SuperH SH4-202 MicroDev board support.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/err.h>
#include <mach/microdev.h>
#define SMSC_CONFIG_PORT_ADDR (0x3F0)
#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
#define SMSC_ENTER_CONFIG_KEY 0x55
#define SMSC_EXIT_CONFIG_KEY 0xaa
#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
#define SMSC_READ_INDEXED(index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
inb(SMSC_DATA_PORT_ADDR); })
#define SMSC_WRITE_INDEXED(val, index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
outb((val), SMSC_DATA_PORT_ADDR); })
#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
#define SERIAL1_PRIMARY_BASE 0x03f8
#define SERIAL2_PRIMARY_BASE 0x02f8
#define MSB(x) ( (x) >> 8 )
#define LSB(x) ( (x) & 0xff )
/* General-Purpose base address on CPU-board FPGA */
#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
static int __init smsc_superio_setup(void)
{
unsigned char devid, devrev;
/* Initially the chip is in run state */
/* Put it into configuration state */
outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
/* Read device ID info */
devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
if ((devid == 0x30) && (devrev == 0x01))
printk("SMSC FDC37C93xAPM SuperIO device detected\n");
else
return -ENODEV;
/* Select the keyboard device */
SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
/* Select the Serial #1 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
/* Select the Serial #2 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#1 device */
SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#2 device */
SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
/* Select the configuration registers */
SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
/* enable the appropriate GPIO pins for IDE functionality:
* bit[0] In/Out 1==input; 0==output
* bit[1] Polarity 1==invert; 0==no invert
* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
* bit[3:4] Function Select 00==original; 01==Alternate Function #1
*/
SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
/* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;
}
device_initcall(smsc_superio_setup);
arch/sh/boards/mach-microdev/irq.c
View file @ 81d6e59d
......@@ -67,27 +67,13 @@ static const struct {
static void enable_microdev_irq(unsigned int irq);
static void disable_microdev_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_microdev_irq disable_microdev_irq
static void mask_and_ack_microdev(unsigned int);
static void end_microdev_irq(unsigned int irq);
static unsigned int startup_microdev_irq(unsigned int irq)
{
enable_microdev_irq(irq);
return 0; /* never anything pending */
}
static struct hw_interrupt_type microdev_irq_type = {
.typename = "MicroDev-IRQ",
.startup = startup_microdev_irq,
.shutdown = shutdown_microdev_irq,
.enable = enable_microdev_irq,
.disable = disable_microdev_irq,
static struct irq_chip microdev_irq_type = {
.name = "MicroDev-IRQ",
.unmask = enable_microdev_irq,
.mask = disable_microdev_irq,
.ack = mask_and_ack_microdev,
.end = end_microdev_irq
};
static void disable_microdev_irq(unsigned int irq)
......@@ -130,11 +116,11 @@ static void enable_microdev_irq(unsigned int irq)
ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
}
/* This functions sets the desired irq handler to be a MicroDev type */
/* This function sets the desired irq handler to be a MicroDev type */
static void __init make_microdev_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &microdev_irq_type;
set_irq_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
disable_microdev_irq(irq);
}
......@@ -143,17 +129,11 @@ static void mask_and_ack_microdev(unsigned int irq)
disable_microdev_irq(irq);
}
static void end_microdev_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_microdev_irq(irq);
}
extern void __init init_microdev_irq(void)
{
int i;
/* disable interrupts on the FPGA INTC register */
/* disable interrupts on the FPGA INTC register */
ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
......@@ -179,5 +159,3 @@ extern void microdev_print_fpga_intc_status(void)
printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
printk("-------------------------------------------------------------------------------\n");
}
arch/sh/boards/mach-microdev/led.c deleted 100644 → 0
View file @ 4a6908a3
/*
* linux/arch/sh/boards/superh/microdev/led.c
*
* Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com>
* Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#include <asm/io.h>
#define LED_REGISTER 0xa6104d20
static void mach_led_d9(int value)
{
unsigned long reg;
reg = ctrl_inl(LED_REGISTER);
reg &= ~1;
reg |= (value & 1);
ctrl_outl(reg, LED_REGISTER);
return;
}
static void mach_led_d10(int value)
{
unsigned long reg;
reg = ctrl_inl(LED_REGISTER);
reg &= ~2;
reg |= ((value & 1) << 1);
ctrl_outl(reg, LED_REGISTER);
return;
}
#ifdef CONFIG_HEARTBEAT
#include <linux/sched.h>
static unsigned char banner_table[] = {
0x11, 0x01, 0x11, 0x01, 0x11, 0x03,
0x11, 0x01, 0x11, 0x01, 0x13, 0x03,
0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03,
0x11, 0x03,
0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07,
0x13, 0x01, 0x13, 0x03,
0x11, 0x01, 0x11, 0x03,
0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
0x13, 0x01, 0x13, 0x01, 0x13, 0x03,
0x13, 0x01, 0x11, 0x01, 0x11, 0x03,
0x11, 0x03,
0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07,
0xff
};
static void banner(void)
{
static int pos = 0;
static int count = 0;
if (count) {
count--;
} else {
int val = banner_table[pos];
if (val == 0xff) {
pos = 0;
val = banner_table[pos];
}
pos++;
mach_led_d10((val >> 4) & 1);
count = 10 * (val & 0xf);
}
}
/* From heartbeat_harp in the stboards directory */
/* acts like an actual heart beat -- ie thump-thump-pause... */
void microdev_heartbeat(void)
{
static unsigned cnt = 0, period = 0, dist = 0;
if (cnt == 0 || cnt == dist)
mach_led_d9(1);
else if (cnt == 7 || cnt == dist+7)
mach_led_d9(0);
if (++cnt > period) {
cnt = 0;
/* The hyperbolic function below modifies the heartbeat period
* length in dependency of the current (5min) load. It goes
* through the points f(0)=126, f(1)=86, f(5)=51,
* f(inf)->30. */
period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
dist = period / 4;
}
banner();
}
#endif
arch/sh/boards/mach-microdev/setup.c
View file @ 81d6e59d
......@@ -17,70 +17,12 @@
#include <mach/microdev.h>
#include <asm/io.h>
#include <asm/machvec.h>
extern void microdev_heartbeat(void);
/****************************************************************************/
/*
* Setup for the SMSC FDC37C93xAPM
*/
#define SMSC_CONFIG_PORT_ADDR (0x3F0)
#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
#define SMSC_ENTER_CONFIG_KEY 0x55
#define SMSC_EXIT_CONFIG_KEY 0xaa
#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
#define SMSC_READ_INDEXED(index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
inb(SMSC_DATA_PORT_ADDR); })
#define SMSC_WRITE_INDEXED(val, index) ({ \
outb((index), SMSC_INDEX_PORT_ADDR); \
outb((val), SMSC_DATA_PORT_ADDR); })
#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
#define SERIAL1_PRIMARY_BASE 0x03f8
#define SERIAL2_PRIMARY_BASE 0x02f8
#define MSB(x) ( (x) >> 8 )
#define LSB(x) ( (x) & 0xff )
/* General-Purpose base address on CPU-board FPGA */
#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
/* assume a Keyboard Controller is present */
int microdev_kbd_controller_present = 1;
#include <asm/sizes.h>
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x300,
.end = 0x300 + 0x0001000 - 1,
.end = 0x300 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
......@@ -97,7 +39,6 @@ static struct platform_device smc91x_device = {
.resource = smc91x_resources,
};
#ifdef CONFIG_FB_S1D13XXX
static struct s1d13xxxfb_regval s1d13806_initregs[] = {
{ S1DREG_MISC, 0x00 },
{ S1DREG_COM_DISP_MODE, 0x00 },
......@@ -216,12 +157,12 @@ static struct s1d13xxxfb_pdata s1d13806_platform_data = {
static struct resource s1d13806_resources[] = {
[0] = {
.start = 0x07200000,
.end = 0x07200000 + 0x00200000 - 1,
.end = 0x07200000 + SZ_2M - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x07000000,
.end = 0x07000000 + 0x00200000 - 1,
.end = 0x07000000 + SZ_2M - 1,
.flags = IORESOURCE_MEM,
},
};
......@@ -236,145 +177,24 @@ static struct platform_device s1d13806_device = {
.platform_data = &s1d13806_platform_data,
},
};
#endif
static struct platform_device *microdev_devices[] __initdata = {
&smc91x_device,
#ifdef CONFIG_FB_S1D13XXX
&s1d13806_device,
#endif
};
static int __init microdev_devices_setup(void)
{
return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
}
/*
* Setup for the SMSC FDC37C93xAPM
*/
static int __init smsc_superio_setup(void)
{
unsigned char devid, devrev;
/* Initially the chip is in run state */
/* Put it into configuration state */
outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
/* Read device ID info */
devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
if ( (devid==0x30) && (devrev==0x01) )
{
printk("SMSC FDC37C93xAPM SuperIO device detected\n");
}
else
{ /* not the device identity we expected */
printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
devid, devrev);
/* inform the keyboard driver that we have no keyboard controller */
microdev_kbd_controller_present = 0;
/* little point in doing anything else in this functon */
return 0;
}
/* Select the keyboard device */
SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
/* Select the Serial #1 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
/* Select the Serial #2 device */
SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
/* enable the interrupts */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#1 device */
SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
/* Select the IDE#2 device */
SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
/* enable it */
SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
/* program with port addresses */
SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
/* select the interrupt */
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
/* Select the configuration registers */
SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
/* enable the appropriate GPIO pins for IDE functionality:
* bit[0] In/Out 1==input; 0==output
* bit[1] Polarity 1==invert; 0==no invert
* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
* bit[3:4] Function Select 00==original; 01==Alternate Function #1
*/
SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
/* Exit the configuration state */
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
return 0;
}
static void __init microdev_setup(char **cmdline_p)
{
int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
const int fpgaRevision = *fpgaRevisionRegister;
int * const CacheControlRegister = (int*)CCR;
device_initcall(microdev_devices_setup);
device_initcall(smsc_superio_setup);
printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
get_system_type(), fpgaRevision, *CacheControlRegister);
}
device_initcall(microdev_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_sh4202_microdev __initmv = {
.mv_name = "SH4-202 MicroDev",
.mv_setup = microdev_setup,
.mv_nr_irqs = 72, /* QQQ need to check this - use the MACRO */
.mv_nr_irqs = 72,
.mv_inb = microdev_inb,
.mv_inw = microdev_inw,
......@@ -398,8 +218,4 @@ static struct sh_machine_vector mv_sh4202_microdev __initmv = {
.mv_outsl = microdev_outsl,
.mv_init_irq = init_microdev_irq,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = microdev_heartbeat,
#endif
};
arch/sh/boards/mach-migor/setup.c
View file @ 81d6e59d
......@@ -89,6 +89,7 @@ static struct resource sh_keysc_resources[] = {
static struct platform_device sh_keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(sh_keysc_resources),
.resource = sh_keysc_resources,
.dev = {
......@@ -261,6 +262,8 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
.sys_bus_cfg = {
.ldmt2r = 0x06000a09,
.ldmt3r = 0x180e3418,
/* set 1s delay to encourage fsync() */
.deferred_io_msec = 1000,
},
}
#endif
......@@ -273,6 +276,10 @@ static struct resource migor_lcdc_resources[] = {
.end = 0xfe941fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 28,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device migor_lcdc_device = {
......@@ -300,6 +307,7 @@ static void camera_power_on(void)
gpio_set_value(GPIO_PTT3, 0);
mdelay(10);
gpio_set_value(GPIO_PTT3, 1);
mdelay(10); /* wait to let chip come out of reset */
}
static void camera_power_off(void)
......@@ -432,6 +440,7 @@ static struct resource migor_ceu_resources[] = {
static struct platform_device migor_ceu_device = {
.name = "sh_mobile_ceu",
.id = 0, /* "ceu0" clock */
.num_resources = ARRAY_SIZE(migor_ceu_resources),
.resource = migor_ceu_resources,
.dev = {
......@@ -479,7 +488,6 @@ static int __init migor_devices_setup(void)
ctrl_outl(0x00110080, BSC_CS4WCR);
/* KEYSC */
clk_always_enable("mstp214"); /* KEYSC */
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
......@@ -501,7 +509,6 @@ static int __init migor_devices_setup(void)
gpio_request(GPIO_FN_IRQ6, NULL);
/* LCD Panel */
clk_always_enable("mstp200"); /* LCDC */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
......@@ -554,7 +561,6 @@ static int __init migor_devices_setup(void)
#endif
/* CEU */
clk_always_enable("mstp203"); /* CEU */
gpio_request(GPIO_FN_VIO_CLK2, NULL);
gpio_request(GPIO_FN_VIO_VD2, NULL);
gpio_request(GPIO_FN_VIO_HD2, NULL);
......@@ -589,12 +595,3 @@ static int __init migor_devices_setup(void)
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);
static void __init migor_setup(char **cmdline_p)
{
}
static struct sh_machine_vector mv_migor __initmv = {
.mv_name = "Migo-R",
.mv_setup = migor_setup,
};
arch/sh/boards/mach-rsk/Kconfig 0 → 100644
View file @ 81d6e59d
if SH_RSK
choice
prompt "RSK+ options"
default SH_RSK7203
config SH_RSK7201
bool "RSK7201"
depends on CPU_SUBTYPE_SH7201
config SH_RSK7203
bool "RSK7203"
select GENERIC_GPIO
depends on CPU_SUBTYPE_SH7203
endchoice
endif
arch/sh/boards/mach-rsk/Makefile 0 → 100644
View file @ 81d6e59d
obj-y := setup.o
obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o
arch/sh/boards/board-rsk7203.c → arch/sh/boards/mach-rsk/devices-rsk7203.c
View file @ 81d6e59d
......@@ -50,73 +50,6 @@ static struct platform_device smc911x_device = {
},
};
static const char *probes[] = { "cmdlinepart", NULL };
static struct mtd_partition *parsed_partitions;
static struct mtd_partition rsk7203_partitions[] = {
{
.name = "Bootloader",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x001c0000,
}, {
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
};
static struct resource flash_resource = {
.start = 0x20000000,
.end = 0x20400000,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct mtd_info *flash_mtd;
static struct map_info rsk7203_flash_map = {
.name = "RSK+ Flash",
.size = 0x400000,
.bankwidth = 2,
};
static void __init set_mtd_partitions(void)
{
int nr_parts = 0;
simple_map_init(&rsk7203_flash_map);
flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map);
nr_parts = parse_mtd_partitions(flash_mtd, probes,
&parsed_partitions, 0);
/* If there is no partition table, used the hard coded table */
if (nr_parts <= 0) {
flash_data.parts = rsk7203_partitions;
flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions);
} else {
flash_data.nr_parts = nr_parts;
flash_data.parts = parsed_partitions;
}
}
static struct gpio_led rsk7203_gpio_leds[] = {
{
.name = "green",
......@@ -155,7 +88,6 @@ static struct platform_device led_device = {
static struct platform_device *rsk7203_devices[] __initdata = {
&smc911x_device,
&flash_device,
&led_device,
};
......@@ -165,15 +97,7 @@ static int __init rsk7203_devices_setup(void)
gpio_request(GPIO_FN_TXD0, NULL);
gpio_request(GPIO_FN_RXD0, NULL);
set_mtd_partitions();
return platform_add_devices(rsk7203_devices,
ARRAY_SIZE(rsk7203_devices));
}
device_initcall(rsk7203_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_rsk7203 __initmv = {
.mv_name = "RSK+7203",
};
arch/sh/boards/mach-rsk/setup.c 0 → 100644
View file @ 81d6e59d
/*
* Renesas Technology Europe RSK+ Support.
*
* Copyright (C) 2008 Paul Mundt
* Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/map.h>
#include <asm/machvec.h>
#include <asm/io.h>
static const char *probes[] = { "cmdlinepart", NULL };
static struct mtd_partition *parsed_partitions;
static struct mtd_partition rsk_partitions[] = {
{
.name = "Bootloader",
.offset = 0x00000000,
.size = 0x00040000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 0x001c0000,
}, {
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
};
static struct resource flash_resource = {
.start = 0x20000000,
.end = 0x20400000,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct mtd_info *flash_mtd;
static struct map_info rsk_flash_map = {
.name = "RSK+ Flash",
.size = 0x400000,
.bankwidth = 2,
};
static void __init set_mtd_partitions(void)
{
int nr_parts = 0;
simple_map_init(&rsk_flash_map);
flash_mtd = do_map_probe("cfi_probe", &rsk_flash_map);
nr_parts = parse_mtd_partitions(flash_mtd, probes,
&parsed_partitions, 0);
/* If there is no partition table, used the hard coded table */
if (nr_parts <= 0) {
flash_data.parts = rsk_partitions;
flash_data.nr_parts = ARRAY_SIZE(rsk_partitions);
} else {
flash_data.nr_parts = nr_parts;
flash_data.parts = parsed_partitions;
}
}
static struct platform_device *rsk_devices[] __initdata = {
&flash_device,
};
static int __init rsk_devices_setup(void)
{
set_mtd_partitions();
return platform_add_devices(rsk_devices,
ARRAY_SIZE(rsk_devices));
}
device_initcall(rsk_devices_setup);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_rsk __initmv = {
.mv_name = "RSK+",
};
arch/sh/boards/mach-se/7343/Makefile
View file @ 81d6e59d
......@@ -2,4 +2,4 @@
# Makefile for the 7343 SolutionEngine specific parts of the kernel
#
obj-y := setup.o io.o irq.o
obj-y := setup.o irq.o
arch/sh/boards/mach-se/7343/io.c deleted 100644 → 0
View file @ 4a6908a3
/*
* arch/sh/boards/se/7343/io.c
*
* I/O routine for SH-Mobile3AS 7343 SolutionEngine.
*
*/
#include <linux/kernel.h>
#include <asm/io.h>
#include <mach-se/mach/se7343.h>
#define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a)
struct iop {
unsigned long start, end;
unsigned long base;
struct iop *(*check) (struct iop * p, unsigned long port);
unsigned char (*inb) (struct iop * p, unsigned long port);
unsigned short (*inw) (struct iop * p, unsigned long port);
void (*outb) (struct iop * p, unsigned char value, unsigned long port);
void (*outw) (struct iop * p, unsigned short value, unsigned long port);
};
struct iop *
simple_check(struct iop *p, unsigned long port)
{
static int count;
if (count < 100)
count++;
port &= 0xFFFF;
if ((p->start <= port) && (port <= p->end))
return p;
else
badio(check, port);
}
struct iop *
ide_check(struct iop *p, unsigned long port)
{
if (((0x1f0 <= port) && (port <= 0x1f7)) || (port == 0x3f7))
return p;
return NULL;
}
unsigned char
simple_inb(struct iop *p, unsigned long port)
{
return *(unsigned char *) (p->base + port);
}
unsigned short
simple_inw(struct iop *p, unsigned long port)
{
return *(unsigned short *) (p->base + port);
}
void
simple_outb(struct iop *p, unsigned char value, unsigned long port)
{
*(unsigned char *) (p->base + port) = value;
}
void
simple_outw(struct iop *p, unsigned short value, unsigned long port)
{
*(unsigned short *) (p->base + port) = value;
}
unsigned char
pcc_inb(struct iop *p, unsigned long port)
{
unsigned long addr = p->base + port + 0x40000;
unsigned long v;
if (port & 1)
addr += 0x00400000;
v = *(volatile unsigned char *) addr;
return v;
}
void
pcc_outb(struct iop *p, unsigned char value, unsigned long port)
{
unsigned long addr = p->base + port + 0x40000;
if (port & 1)
addr += 0x00400000;
*(volatile unsigned char *) addr = value;
}
unsigned char
bad_inb(struct iop *p, unsigned long port)
{
badio(inb, port);
}
void
bad_outb(struct iop *p, unsigned char value, unsigned long port)
{
badio(inw, port);
}
#ifdef CONFIG_SMC91X
/* MSTLANEX01 LAN at 0xb400:0000 */
static struct iop laniop = {
.start = 0x00,
.end = 0x0F,
.base = 0x04000000,
.check = simple_check,
.inb = simple_inb,
.inw = simple_inw,
.outb = simple_outb,
.outw = simple_outw,
};
#endif
#ifdef CONFIG_NE2000
/* NE2000 pc card NIC */
static struct iop neiop = {
.start = 0x280,
.end = 0x29f,
.base = 0xb0600000 + 0x80, /* soft 0x280 -> hard 0x300 */
.check = simple_check,
.inb = pcc_inb,
.inw = simple_inw,
.outb = pcc_outb,
.outw = simple_outw,
};
#endif
#ifdef CONFIG_IDE
/* CF in CF slot */
static struct iop cfiop = {
.base = 0xb0600000,
.check = ide_check,
.inb = pcc_inb,
.inw = simple_inw,
.outb = pcc_outb,
.outw = simple_outw,
};
#endif
static __inline__ struct iop *
port2iop(unsigned long port)
{
if (0) ;
#if defined(CONFIG_SMC91X)
else if (laniop.check(&laniop, port))
return &laniop;
#endif
#if defined(CONFIG_NE2000)
else if (neiop.check(&neiop, port))
return &neiop;
#endif
#if defined(CONFIG_IDE)
else if (cfiop.check(&cfiop, port))
return &cfiop;
#endif
else
return NULL;
}
static inline void
delay(void)
{
ctrl_inw(0xac000000);
ctrl_inw(0xac000000);
}
unsigned char
sh7343se_inb(unsigned long port)
{
struct iop *p = port2iop(port);
return (p->inb) (p, port);
}
unsigned char
sh7343se_inb_p(unsigned long port)
{
unsigned char v = sh7343se_inb(port);
delay();
return v;
}
unsigned short
sh7343se_inw(unsigned long port)
{
struct iop *p = port2iop(port);
return (p->inw) (p, port);
}
unsigned int
sh7343se_inl(unsigned long port)
{
badio(inl, port);
}
void
sh7343se_outb(unsigned char value, unsigned long port)
{
struct iop *p = port2iop(port);
(p->outb) (p, value, port);
}
void
sh7343se_outb_p(unsigned char value, unsigned long port)
{
sh7343se_outb(value, port);
delay();
}
void
sh7343se_outw(unsigned short value, unsigned long port)
{
struct iop *p = port2iop(port);
(p->outw) (p, value, port);
}
void
sh7343se_outl(unsigned int value, unsigned long port)
{
badio(outl, port);
}
void
sh7343se_insb(unsigned long port, void *addr, unsigned long count)
{
unsigned char *a = addr;
struct iop *p = port2iop(port);
while (count--)
*a++ = (p->inb) (p, port);
}
void
sh7343se_insw(unsigned long port, void *addr, unsigned long count)
{
unsigned short *a = addr;
struct iop *p = port2iop(port);
while (count--)
*a++ = (p->inw) (p, port);
}
void
sh7343se_insl(unsigned long port, void *addr, unsigned long count)
{
badio(insl, port);
}
void
sh7343se_outsb(unsigned long port, const void *addr, unsigned long count)
{
unsigned char *a = (unsigned char *) addr;
struct iop *p = port2iop(port);
while (count--)
(p->outb) (p, *a++, port);
}
void
sh7343se_outsw(unsigned long port, const void *addr, unsigned long count)
{
unsigned short *a = (unsigned short *) addr;
struct iop *p = port2iop(port);
while (count--)
(p->outw) (p, *a++, port);
}
void
sh7343se_outsl(unsigned long port, const void *addr, unsigned long count)
{
badio(outsw, port);
}
arch/sh/boards/mach-se/7343/setup.c
View file @ 81d6e59d
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/usb/isp116x.h>
#include <linux/delay.h>
#include <asm/machvec.h>
#include <mach-se/mach/se7343.h>
#include <asm/heartbeat.h>
#include <asm/irq.h>
#include <asm/io.h>
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x10000000,
.end = 0x1000000F,
.flags = IORESOURCE_MEM,
},
[1] = {
/*
* shared with other devices via externel
* interrupt controller in FPGA...
*/
.start = SMC_IRQ,
.end = SMC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
......@@ -94,10 +74,83 @@ static struct platform_device nor_flash_device = {
.resource = nor_flash_resources,
};
#define ST16C2550C_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP)
static struct plat_serial8250_port serial_platform_data[] = {
[0] = {
.iotype = UPIO_MEM,
.mapbase = 0x16000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.irq = UARTA_IRQ,
.uartclk = 7372800,
},
[1] = {
.iotype = UPIO_MEM,
.mapbase = 0x17000000,
.regshift = 1,
.flags = ST16C2550C_FLAGS,
.irq = UARTB_IRQ,
.uartclk = 7372800,
},
{ },
};
static struct platform_device uart_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
static void isp116x_delay(struct device *dev, int delay)
{
ndelay(delay);
}
static struct resource usb_resources[] = {
[0] = {
.start = 0x11800000,
.end = 0x11800001,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x11800002,
.end = 0x11800003,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = USB_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct isp116x_platform_data usb_platform_data = {
.sel15Kres = 1,
.oc_enable = 1,
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_enable = 0,
.delay = isp116x_delay,
};
static struct platform_device usb_device = {
.name = "isp116x-hcd",
.id = -1,
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
.dev = {
.platform_data = &usb_platform_data,
},
};
static struct platform_device *sh7343se_platform_devices[] __initdata = {
&smc91x_device,
&heartbeat_device,
&nor_flash_device,
&uart_device,
&usb_device,
};
static int __init sh7343se_devices_setup(void)
......@@ -126,27 +179,6 @@ static void __init sh7343se_setup(char **cmdline_p)
static struct sh_machine_vector mv_7343se __initmv = {
.mv_name = "SolutionEngine 7343",
.mv_setup = sh7343se_setup,
.mv_nr_irqs = 108,
.mv_inb = sh7343se_inb,
.mv_inw = sh7343se_inw,
.mv_inl = sh7343se_inl,
.mv_outb = sh7343se_outb,
.mv_outw = sh7343se_outw,
.mv_outl = sh7343se_outl,
.mv_inb_p = sh7343se_inb_p,
.mv_inw_p = sh7343se_inw,
.mv_inl_p = sh7343se_inl,
.mv_outb_p = sh7343se_outb_p,
.mv_outw_p = sh7343se_outw,
.mv_outl_p = sh7343se_outl,
.mv_insb = sh7343se_insb,
.mv_insw = sh7343se_insw,
.mv_insl = sh7343se_insl,
.mv_outsb = sh7343se_outsb,
.mv_outsw = sh7343se_outsw,
.mv_outsl = sh7343se_outsl,
.mv_nr_irqs = SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_NR,
.mv_init_irq = init_7343se_IRQ,
};
arch/sh/boards/mach-se/770x/setup.c
View file @ 81d6e59d
......@@ -8,8 +8,9 @@
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <mach-se/mach/se.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/smc37c93x.h>
#include <asm/heartbeat.h>
......@@ -175,6 +176,7 @@ static struct platform_device *se_devices[] __initdata = {
static int __init se_devices_setup(void)
{
mrshpc_setup_windows();
return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
}
device_initcall(se_devices_setup);
......
arch/sh/boards/mach-se/7721/setup.c
View file @ 81d6e59d
......@@ -12,8 +12,9 @@
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <mach-se/mach/se7721.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
......@@ -74,8 +75,8 @@ static struct platform_device *se7721_devices[] __initdata = {
static int __init se7721_devices_setup(void)
{
return platform_add_devices(se7721_devices,
ARRAY_SIZE(se7721_devices));
mrshpc_setup_windows();
return platform_add_devices(se7721_devices, ARRAY_SIZE(se7721_devices));
}
device_initcall(se7721_devices_setup);
......
arch/sh/boards/mach-se/7722/setup.c
View file @ 81d6e59d
......@@ -15,9 +15,10 @@
#include <linux/ata_platform.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach-se/mach/se7722.h>
#include <mach-se/mach/mrshpc.h>
#include <asm/machvec.h>
#include <asm/clock.h>
#include <mach-se/mach/se7722.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
#include <asm/sh_keysc.h>
......@@ -130,6 +131,7 @@ static struct resource sh_keysc_resources[] = {
static struct platform_device sh_keysc_device = {
.name = "sh_keysc",
.id = 0, /* "keysc0" clock */
.num_resources = ARRAY_SIZE(sh_keysc_resources),
.resource = sh_keysc_resources,
.dev = {
......@@ -146,10 +148,8 @@ static struct platform_device *se7722_devices[] __initdata = {
static int __init se7722_devices_setup(void)
{
clk_always_enable("mstp214"); /* KEYSC */
return platform_add_devices(se7722_devices,
ARRAY_SIZE(se7722_devices));
mrshpc_setup_windows();
return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
}
device_initcall(se7722_devices_setup);
......
arch/sh/boards/mach-sh03/setup.c
View file @ 81d6e59d
......@@ -9,6 +9,7 @@
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <mach-sh03/mach/io.h>
......@@ -20,19 +21,6 @@ static void __init init_sh03_IRQ(void)
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
extern void *cf_io_base;
static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size)
{
if (PXSEG(port))
return (void __iomem *)port;
/* CompactFlash (IDE) */
if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6))
return (void __iomem *)((unsigned long)cf_io_base + port);
return (void __iomem *)(port + PCI_IO_BASE);
}
/* arch/sh/boards/sh03/rtc.c */
void sh03_time_init(void);
......@@ -41,6 +29,30 @@ static void __init sh03_setup(char **cmdline_p)
board_time_init = sh03_time_init;
}
static struct resource cf_ide_resources[] = {
[0] = {
.start = 0x1f0,
.end = 0x1f0 + 8,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 0x1f0 + 0x206,
.end = 0x1f0 +8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
.start = IRL2_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xa0800000,
......@@ -58,10 +70,30 @@ static struct platform_device heartbeat_device = {
static struct platform_device *sh03_devices[] __initdata = {
&heartbeat_device,
&cf_ide_device,
};
static int __init sh03_devices_setup(void)
{
pgprot_t prot;
unsigned long paddrbase;
void *cf_ide_base;
/* open I/O area window */
paddrbase = virt_to_phys((void *)PA_AREA5_IO);
prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot);
if (!cf_ide_base) {
printk("allocate_cf_area : can't open CF I/O window!\n");
return -ENOMEM;
}
/* IDE cmd address : 0x1f0-0x1f7 and 0x3f6 */
cf_ide_resources[0].start += (unsigned long)cf_ide_base;
cf_ide_resources[0].end += (unsigned long)cf_ide_base;
cf_ide_resources[1].start += (unsigned long)cf_ide_base;
cf_ide_resources[1].end += (unsigned long)cf_ide_base;
return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices));
}
__initcall(sh03_devices_setup);
......@@ -70,6 +102,5 @@ static struct sh_machine_vector mv_sh03 __initmv = {
.mv_name = "Interface (CTP/PCI-SH03)",
.mv_setup = sh03_setup,
.mv_nr_irqs = 48,
.mv_ioport_map = sh03_ioport_map,
.mv_init_irq = init_sh03_IRQ,
};
arch/sh/boards/mach-systemh/irq.c
View file @ 81d6e59d
......@@ -12,8 +12,8 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/io.h>
#include <mach/systemh7751.h>
#include <asm/smc37c93x.h>
......@@ -24,35 +24,17 @@ static unsigned long *systemh_irq_mask_register = (unsigned long *)0xB3F10004;
static unsigned long *systemh_irq_request_register = (unsigned long *)0xB3F10000;
/* forward declaration */
static unsigned int startup_systemh_irq(unsigned int irq);
static void shutdown_systemh_irq(unsigned int irq);
static void enable_systemh_irq(unsigned int irq);
static void disable_systemh_irq(unsigned int irq);
static void mask_and_ack_systemh(unsigned int);
static void end_systemh_irq(unsigned int irq);
/* hw_interrupt_type */
static struct hw_interrupt_type systemh_irq_type = {
.typename = " SystemH Register",
.startup = startup_systemh_irq,
.shutdown = shutdown_systemh_irq,
.enable = enable_systemh_irq,
.disable = disable_systemh_irq,
static struct irq_chip systemh_irq_type = {
.name = " SystemH Register",
.unmask = enable_systemh_irq,
.mask = disable_systemh_irq,
.ack = mask_and_ack_systemh,
.end = end_systemh_irq
};
static unsigned int startup_systemh_irq(unsigned int irq)
{
enable_systemh_irq(irq);
return 0; /* never anything pending */
}
static void shutdown_systemh_irq(unsigned int irq)
{
disable_systemh_irq(irq);
}
static void disable_systemh_irq(unsigned int irq)
{
if (systemh_irq_mask_register) {
......@@ -86,16 +68,9 @@ static void mask_and_ack_systemh(unsigned int irq)
disable_systemh_irq(irq);
}
static void end_systemh_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_systemh_irq(irq);
}
void make_systemh_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &systemh_irq_type;
set_irq_chip_and_handler(irq, &systemh_irq_type, handle_level_irq);
disable_systemh_irq(irq);
}
arch/sh/cchips/hd6446x/hd64461.c
View file @ 81d6e59d
......@@ -10,99 +10,49 @@
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hd64461.h>
/* This belongs in cpu specific */
#define INTC_ICR1 0xA4140010UL
static void disable_hd64461_irq(unsigned int irq)
static void hd64461_mask_irq(unsigned int irq)
{
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64461_IRQBASE);
nimr = inw(HD64461_NIMR);
nimr = __raw_readw(HD64461_NIMR);
nimr |= mask;
outw(nimr, HD64461_NIMR);
__raw_writew(nimr, HD64461_NIMR);
}
static void enable_hd64461_irq(unsigned int irq)
static void hd64461_unmask_irq(unsigned int irq)
{
unsigned short nimr;
unsigned short mask = 1 << (irq - HD64461_IRQBASE);
nimr = inw(HD64461_NIMR);
nimr = __raw_readw(HD64461_NIMR);
nimr &= ~mask;
outw(nimr, HD64461_NIMR);
__raw_writew(nimr, HD64461_NIMR);
}
static void mask_and_ack_hd64461(unsigned int irq)
static void hd64461_mask_and_ack_irq(unsigned int irq)
{
disable_hd64461_irq(irq);
hd64461_mask_irq(irq);
#ifdef CONFIG_HD64461_ENABLER
if (irq == HD64461_IRQBASE + 13)
outb(0x00, HD64461_PCC1CSCR);
__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif
}
static void end_hd64461_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_hd64461_irq(irq);
}
static unsigned int startup_hd64461_irq(unsigned int irq)
{
enable_hd64461_irq(irq);
return 0;
}
static void shutdown_hd64461_irq(unsigned int irq)
{
disable_hd64461_irq(irq);
}
static struct hw_interrupt_type hd64461_irq_type = {
.typename = "HD64461-IRQ",
.startup = startup_hd64461_irq,
.shutdown = shutdown_hd64461_irq,
.enable = enable_hd64461_irq,
.disable = disable_hd64461_irq,
.ack = mask_and_ack_hd64461,
.end = end_hd64461_irq,
static struct irq_chip hd64461_irq_chip = {
.name = "HD64461-IRQ",
.mask = hd64461_mask_irq,
.mask_ack = hd64461_mask_and_ack_irq,
.unmask = hd64461_unmask_irq,
};
static irqreturn_t hd64461_interrupt(int irq, void *dev_id)
{
printk(KERN_INFO
"HD64461: spurious interrupt, nirr: 0x%x nimr: 0x%x\n",
inw(HD64461_NIRR), inw(HD64461_NIMR));
return IRQ_NONE;
}
static struct {
int (*func) (int, void *);
void *dev;
} hd64461_demux[HD64461_IRQ_NUM];
void hd64461_register_irq_demux(int irq,
int (*demux) (int irq, void *dev), void *dev)
{
hd64461_demux[irq - HD64461_IRQBASE].func = demux;
hd64461_demux[irq - HD64461_IRQBASE].dev = dev;
}
EXPORT_SYMBOL(hd64461_register_irq_demux);
void hd64461_unregister_irq_demux(int irq)
{
hd64461_demux[irq - HD64461_IRQBASE].func = 0;
}
EXPORT_SYMBOL(hd64461_unregister_irq_demux);
int hd64461_irq_demux(int irq)
{
if (irq == CONFIG_HD64461_IRQ) {
......@@ -115,25 +65,11 @@ int hd64461_irq_demux(int irq)
for (bit = 1, i = 0; i < 16; bit <<= 1, i++)
if (nirr & bit)
break;
if (i == 16)
irq = CONFIG_HD64461_IRQ;
else {
irq = HD64461_IRQBASE + i;
if (hd64461_demux[i].func != 0) {
irq = hd64461_demux[i].func(irq, hd64461_demux[i].dev);
}
}
irq = HD64461_IRQBASE + i;
}
return irq;
}
static struct irqaction irq0 = {
.handler = hd64461_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "HD64461",
};
int __init setup_hd64461(void)
{
int i;
......@@ -146,22 +82,21 @@ int __init setup_hd64461(void)
CONFIG_HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
HD64461_IRQBASE + 15);
#if defined(CONFIG_CPU_SUBTYPE_SH7709) /* Should be at processor specific part.. */
outw(0x2240, INTC_ICR1);
/* Should be at processor specific part.. */
#if defined(CONFIG_CPU_SUBTYPE_SH7709)
__raw_writew(0x2240, INTC_ICR1);
#endif
outw(0xffff, HD64461_NIMR);
__raw_writew(0xffff, HD64461_NIMR);
/* IRQ 80 -> 95 belongs to HD64461 */
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
irq_desc[i].chip = &hd64461_irq_type;
}
setup_irq(CONFIG_HD64461_IRQ, &irq0);
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
set_irq_chip_and_handler(i, &hd64461_irq_chip,
handle_level_irq);
#ifdef CONFIG_HD64461_ENABLER
printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
outb(0x4c, HD64461_PCC1CSCIER);
outb(0x00, HD64461_PCC1CSCR);
__raw_writeb(0x4c, HD64461_PCC1CSCIER);
__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif
return 0;
......
arch/sh/configs/edosk7705_defconfig 0 → 100644
View file @ 81d6e59d
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc6
# Wed Dec 17 13:53:02 2008
#
CONFIG_SUPERH=y
CONFIG_SUPERH32=y
CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_GENERIC_IRQ_PROBE=y
# CONFIG_GENERIC_GPIO is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
# CONFIG_UID16 is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PRINTK is not set
# CONFIG_BUG is not set
# CONFIG_ELF_CORE is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
CONFIG_SHMEM=y
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
# CONFIG_MODULES is not set
# CONFIG_BLOCK is not set
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
# System type
#
CONFIG_CPU_SH3=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7201 is not set
# CONFIG_CPU_SUBTYPE_SH7203 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7263 is not set
# CONFIG_CPU_SUBTYPE_MXG is not set
CONFIG_CPU_SUBTYPE_SH7705=y
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7721 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
# CONFIG_CPU_SUBTYPE_SH7750S is not set
# CONFIG_CPU_SUBTYPE_SH7751 is not set
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
# CONFIG_CPU_SUBTYPE_SH7723 is not set
# CONFIG_CPU_SUBTYPE_SH7763 is not set
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
# CONFIG_CPU_SUBTYPE_SH7366 is not set
# CONFIG_CPU_SUBTYPE_SH5_101 is not set
# CONFIG_CPU_SUBTYPE_SH5_103 is not set
#
# Memory management options
#
CONFIG_QUICKLIST=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_MEMORY_START=0x08000000
CONFIG_MEMORY_SIZE=0x04000000
CONFIG_29BIT=y
CONFIG_VSYSCALL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_ENTRY_OFFSET=0x00001000
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
# CONFIG_DISCONTIGMEM_MANUAL is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MIGRATION=y
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_NR_QUICK=2
CONFIG_UNEVICTABLE_LRU=y
#
# Cache configuration
#
CONFIG_SH7705_CACHE_32KB=y
# CONFIG_SH_DIRECT_MAPPED is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SH_ADC=y
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_SR_RB=y
#
# Board support
#
# CONFIG_SH_SOLUTION_ENGINE is not set
CONFIG_SH_EDOSK7705=y
#
# Timer and clock configuration
#
CONFIG_SH_TMU=y
CONFIG_SH_TIMER_IRQ=16
CONFIG_SH_PCLK_FREQ=31250000
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# DMA support
#
# CONFIG_SH_DMA is not set
#
# Companion Chips
#
#
# Additional SuperH Device Drivers
#
# CONFIG_HEARTBEAT is not set
# CONFIG_PUSH_SWITCH is not set
#
# Kernel features
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_GUSA=y
# CONFIG_GUSA_RB is not set
#
# Boot options
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_CMDLINE_BOOL is not set
#
# Bus options
#
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_NET is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
#
# SCSI device support
#
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_PHONE is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_SH_SCI is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_SOUND is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
CONFIG_STAGING_EXCLUDE_BUILD=y
#
# File systems
#
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# Pseudo filesystems
#
# CONFIG_PROC_FS is not set
# CONFIG_SYSFS is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
#
# Miscellaneous filesystems
#
# CONFIG_NLS is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
#
# Tracers
#
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_MORE_COMPILE_OPTIONS is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC32 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
arch/sh/configs/rsk7203_defconfig
View file @ 81d6e59d
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.27
# Tue Oct 21 12:58:47 2008
# Linux kernel version: 2.6.28-rc6
# Mon Dec 8 14:35:03 2008
#
CONFIG_SUPERH=y
CONFIG_SUPERH32=y
......@@ -16,6 +16,8 @@ CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
......@@ -75,7 +77,6 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_AIO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
# CONFIG_SLAB is not set
# CONFIG_SLUB is not set
CONFIG_SLOB=y
......@@ -126,6 +127,7 @@ CONFIG_CLASSIC_RCU=y
CONFIG_CPU_SH2=y
CONFIG_CPU_SH2A=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7201 is not set
CONFIG_CPU_SUBTYPE_SH7203=y
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7263 is not set
......@@ -211,6 +213,8 @@ CONFIG_CPU_HAS_FPU=y
#
# Board support
#
CONFIG_SH_RSK=y
# CONFIG_SH_RSK7201 is not set
CONFIG_SH_RSK7203=y
#
......@@ -296,6 +300,14 @@ CONFIG_BINFMT_ZFLAT=y
CONFIG_BINFMT_SHARED_FLAT=y
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options (EXPERIMENTAL)
#
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_NET=y
#
......@@ -477,6 +489,7 @@ CONFIG_BLK_DEV=y
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_C2PORT is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
......@@ -603,11 +616,11 @@ CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
......@@ -617,7 +630,11 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_WM8400 is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
#
# Multimedia devices
......@@ -702,19 +719,22 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_SUSPEND is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
CONFIG_USB_MON=y
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_SL811_HCD is not set
CONFIG_USB_R8A66597_HCD=y
# CONFIG_USB_HWA_HCD is not set
#
# USB Device Class drivers
......@@ -725,11 +745,11 @@ CONFIG_USB_R8A66597_HCD=y
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
#
#
# may also be needed; see USB_STORAGE Help for more information
# see USB_STORAGE Help for more information
#
# CONFIG_USB_LIBUSUAL is not set
......@@ -770,7 +790,22 @@ CONFIG_USB_R8A66597_HCD=y
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
CONFIG_LEDS_GPIO=y
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
......@@ -812,6 +847,7 @@ CONFIG_RTC_DRV_SH=y
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
CONFIG_STAGING_EXCLUDE_BUILD=y
#
# File systems
......@@ -950,9 +986,14 @@ CONFIG_FRAME_POINTER=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FTRACE=y
# CONFIG_FTRACE is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_BOOT_TRACER is not set
......
arch/sh/configs/se7343_defconfig
View file @ 81d6e59d
This diff is collapsed.
arch/sh/drivers/dma/Makefile
View file @ 81d6e59d
......@@ -3,7 +3,6 @@
#
obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o
obj-$(CONFIG_ISA_DMA_API) += dma-isa.o
obj-$(CONFIG_SH_DMA) += dma-sh.o
obj-$(CONFIG_SH_DREAMCAST) += dma-pvr2.o dma-g2.o
obj-$(CONFIG_SH_DMABRG) += dmabrg.o
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arch/sh/drivers/dma/dma-sh.c
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......@@ -205,7 +205,8 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
#define dmaor_read_reg() ctrl_inw(DMAOR)
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
#else
......
arch/sh/drivers/dma/dma-sh.h
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......@@ -29,6 +29,7 @@
#define RS_IN 0x00000200
#define RS_OUT 0x00000300
#define TS_BLK 0x00000040
#define TM_BUR 0x00000020
#define CHCR_DE 0x00000001
#define CHCR_TE 0x00000002
#define CHCR_IE 0x00000004
......
arch/sh/drivers/pci/ops-sh03.c
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......@@ -18,7 +18,8 @@
*/
int __init pcibios_init_platform(void)
{
return 1;
__set_io_port_base(SH7751_PCI_IO_BASE);
return 1;
}
static struct resource sh7751_io_resource = {
......
arch/sh/drivers/pci/pci-sh7780.c
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......@@ -123,16 +123,14 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
* Window0 = map->window0.size @ non-cached area base = SDRAM
* Window1 = map->window1.size @ cached area base = SDRAM
*/
word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
pci_write_reg(0x07f00001, SH4_PCILSR0);
word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
word = (CONFIG_MEMORY_SIZE - 0x00100000) | 0x00000001;
pci_write_reg(word, SH4_PCILSR0);
pci_write_reg(0x00000001, SH4_PCILSR1);
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(map->window0.base);
pci_write_reg(0xa8000000, SH4_PCILAR0);
pci_write_reg(0x08000000, SH7780_PCIMBAR0);
word = (CONFIG_MEMORY_SIZE > 0x08000000) ? 0x10000000 : 0x08000000;
pci_write_reg(word | 0xa0000000, SH4_PCILAR0);
pci_write_reg(word, SH7780_PCIMBAR0);
/* Set the values on window 1 PCI config registers */
word = P2SEGADDR(map->window1.base);
pci_write_reg(0x00000000, SH4_PCILAR1);
pci_write_reg(0x00000000, SH7780_PCIMBAR1);
......
arch/sh/include/asm/addrspace.h
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......@@ -49,5 +49,16 @@
/* Check if an address can be reached in 29 bits */
#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
#ifdef CONFIG_SH_STORE_QUEUES
/*
* This is a special case for the SH-4 store queues, as pages for this
* space still need to be faulted in before it's possible to flush the
* store queue cache for writeout to the remapped region.
*/
#define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000)
#else
#define P3_ADDR_MAX P4SEG
#endif
#endif /* __KERNEL__ */
#endif /* __ASM_SH_ADDRSPACE_H */
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......@@ -166,4 +166,7 @@ static inline int test_and_change_bit(int nr, volatile void * addr)
return retval;
}
#include <asm-generic/bitops/non-atomic.h>
#endif /* __ASM_SH_BITOPS_GRB_H */
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return retval != 0;
}
#include <asm-generic/bitops/non-atomic.h>
#endif /* __ASM_SH_BITOPS_LLSC_H */
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