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Commit 86037742 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/disp/tu102: rename implementation from tu104 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 954f9798
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Showing with 43 additions and 43 deletions
drivers/gpu/drm/nouveau/dispnv50/core.c
View file @ 86037742
...@@ -42,7 +42,7 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore) ...@@ -42,7 +42,7 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
int version; int version;
int (*new)(struct nouveau_drm *, s32, struct nv50_core **); int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
} cores[] = { } cores[] = {
{ TU104_DISP_CORE_CHANNEL_DMA, 0, corec57d_new }, { TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new }, { GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new }, { GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
{ GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new }, { GP100_DISP_CORE_CHANNEL_DMA, 0, core917d_new },
......
drivers/gpu/drm/nouveau/dispnv50/curs.c
View file @ 86037742
...@@ -31,7 +31,7 @@ nv50_curs_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw) ...@@ -31,7 +31,7 @@ nv50_curs_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)
int version; int version;
int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **); int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **);
} curses[] = { } curses[] = {
{ TU104_DISP_CURSOR, 0, cursc37a_new }, { TU102_DISP_CURSOR, 0, cursc37a_new },
{ GV100_DISP_CURSOR, 0, cursc37a_new }, { GV100_DISP_CURSOR, 0, cursc37a_new },
{ GK104_DISP_CURSOR, 0, curs907a_new }, { GK104_DISP_CURSOR, 0, curs907a_new },
{ GF110_DISP_CURSOR, 0, curs907a_new }, { GF110_DISP_CURSOR, 0, curs907a_new },
......
drivers/gpu/drm/nouveau/dispnv50/wimm.c
View file @ 86037742
...@@ -31,7 +31,7 @@ nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw) ...@@ -31,7 +31,7 @@ nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw)
int version; int version;
int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *); int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
} wimms[] = { } wimms[] = {
{ TU104_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init }, { TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init }, { GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
{} {}
}; };
......
drivers/gpu/drm/nouveau/dispnv50/wndw.c
View file @ 86037742
...@@ -626,7 +626,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, ...@@ -626,7 +626,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
int (*new)(struct nouveau_drm *, enum drm_plane_type, int (*new)(struct nouveau_drm *, enum drm_plane_type,
int, s32, struct nv50_wndw **); int, s32, struct nv50_wndw **);
} wndws[] = { } wndws[] = {
{ TU104_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
{} {}
}; };
......
drivers/gpu/drm/nouveau/include/nvif/class.h
View file @ 86037742
...@@ -84,7 +84,7 @@ ...@@ -84,7 +84,7 @@
#define GP100_DISP /* cl5070.h */ 0x00009770 #define GP100_DISP /* cl5070.h */ 0x00009770
#define GP102_DISP /* cl5070.h */ 0x00009870 #define GP102_DISP /* cl5070.h */ 0x00009870
#define GV100_DISP /* cl5070.h */ 0x0000c370 #define GV100_DISP /* cl5070.h */ 0x0000c370
#define TU104_DISP /* cl5070.h */ 0x0000c570 #define TU102_DISP /* cl5070.h */ 0x0000c570
#define NV31_MPEG 0x00003174 #define NV31_MPEG 0x00003174
#define G82_MPEG 0x00008274 #define G82_MPEG 0x00008274
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
#define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a #define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a
#define TU104_DISP_CURSOR /* cl507a.h */ 0x0000c57a #define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a
#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
...@@ -106,7 +106,7 @@ ...@@ -106,7 +106,7 @@
#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b
#define TU104_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b
#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
#define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d #define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d
#define TU104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d #define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
...@@ -139,7 +139,7 @@ ...@@ -139,7 +139,7 @@
#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
#define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e #define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e
#define TU104_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e #define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e
#define NV50_TESLA 0x00005097 #define NV50_TESLA 0x00005097
#define G82_TESLA 0x00008297 #define G82_TESLA 0x00008297
......
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
View file @ 86037742
...@@ -36,5 +36,5 @@ int gm200_disp_new(struct nvkm_device *, int, struct nvkm_disp **); ...@@ -36,5 +36,5 @@ int gm200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gp100_disp_new(struct nvkm_device *, int, struct nvkm_disp **); int gp100_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gp102_disp_new(struct nvkm_device *, int, struct nvkm_disp **); int gp102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int gv100_disp_new(struct nvkm_device *, int, struct nvkm_disp **); int gv100_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
int tu104_disp_new(struct nvkm_device *, int, struct nvkm_disp **); int tu102_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
#endif #endif
drivers/gpu/drm/nouveau/nvif/disp.c
View file @ 86037742
...@@ -34,7 +34,7 @@ int ...@@ -34,7 +34,7 @@ int
nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp)
{ {
static const struct nvif_mclass disps[] = { static const struct nvif_mclass disps[] = {
{ TU104_DISP, -1 }, { TU102_DISP, -1 },
{ GV100_DISP, -1 }, { GV100_DISP, -1 },
{ GP102_DISP, -1 }, { GP102_DISP, -1 },
{ GP100_DISP, -1 }, { GP100_DISP, -1 },
......
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ 86037742
...@@ -2461,7 +2461,7 @@ nv162_chipset = { ...@@ -2461,7 +2461,7 @@ nv162_chipset = {
.ce[2] = tu104_ce_new, .ce[2] = tu104_ce_new,
.ce[3] = tu104_ce_new, .ce[3] = tu104_ce_new,
.ce[4] = tu104_ce_new, .ce[4] = tu104_ce_new,
.disp = tu104_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu104_fifo_new, .fifo = tu104_fifo_new,
}; };
...@@ -2493,7 +2493,7 @@ nv164_chipset = { ...@@ -2493,7 +2493,7 @@ nv164_chipset = {
.ce[2] = tu104_ce_new, .ce[2] = tu104_ce_new,
.ce[3] = tu104_ce_new, .ce[3] = tu104_ce_new,
.ce[4] = tu104_ce_new, .ce[4] = tu104_ce_new,
.disp = tu104_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu104_fifo_new, .fifo = tu104_fifo_new,
}; };
...@@ -2525,7 +2525,7 @@ nv166_chipset = { ...@@ -2525,7 +2525,7 @@ nv166_chipset = {
.ce[2] = tu104_ce_new, .ce[2] = tu104_ce_new,
.ce[3] = tu104_ce_new, .ce[3] = tu104_ce_new,
.ce[4] = tu104_ce_new, .ce[4] = tu104_ce_new,
.disp = tu104_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu104_fifo_new, .fifo = tu104_fifo_new,
}; };
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
View file @ 86037742
...@@ -15,7 +15,7 @@ nvkm-y += nvkm/engine/disp/gm200.o ...@@ -15,7 +15,7 @@ nvkm-y += nvkm/engine/disp/gm200.o
nvkm-y += nvkm/engine/disp/gp100.o nvkm-y += nvkm/engine/disp/gp100.o
nvkm-y += nvkm/engine/disp/gp102.o nvkm-y += nvkm/engine/disp/gp102.o
nvkm-y += nvkm/engine/disp/gv100.o nvkm-y += nvkm/engine/disp/gv100.o
nvkm-y += nvkm/engine/disp/tu104.o nvkm-y += nvkm/engine/disp/tu102.o
nvkm-y += nvkm/engine/disp/vga.o nvkm-y += nvkm/engine/disp/vga.o
nvkm-y += nvkm/engine/disp/head.o nvkm-y += nvkm/engine/disp/head.o
...@@ -39,7 +39,7 @@ nvkm-y += nvkm/engine/disp/sorgk104.o ...@@ -39,7 +39,7 @@ nvkm-y += nvkm/engine/disp/sorgk104.o
nvkm-y += nvkm/engine/disp/sorgm107.o nvkm-y += nvkm/engine/disp/sorgm107.o
nvkm-y += nvkm/engine/disp/sorgm200.o nvkm-y += nvkm/engine/disp/sorgm200.o
nvkm-y += nvkm/engine/disp/sorgv100.o nvkm-y += nvkm/engine/disp/sorgv100.o
nvkm-y += nvkm/engine/disp/sortu104.o nvkm-y += nvkm/engine/disp/sortu102.o
nvkm-y += nvkm/engine/disp/outp.o nvkm-y += nvkm/engine/disp/outp.o
nvkm-y += nvkm/engine/disp/dp.o nvkm-y += nvkm/engine/disp/dp.o
...@@ -71,7 +71,7 @@ nvkm-y += nvkm/engine/disp/rootgm200.o ...@@ -71,7 +71,7 @@ nvkm-y += nvkm/engine/disp/rootgm200.o
nvkm-y += nvkm/engine/disp/rootgp100.o nvkm-y += nvkm/engine/disp/rootgp100.o
nvkm-y += nvkm/engine/disp/rootgp102.o nvkm-y += nvkm/engine/disp/rootgp102.o
nvkm-y += nvkm/engine/disp/rootgv100.o nvkm-y += nvkm/engine/disp/rootgv100.o
nvkm-y += nvkm/engine/disp/roottu104.o nvkm-y += nvkm/engine/disp/roottu102.o
nvkm-y += nvkm/engine/disp/channv50.o nvkm-y += nvkm/engine/disp/channv50.o
nvkm-y += nvkm/engine/disp/changf119.o nvkm-y += nvkm/engine/disp/changf119.o
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
View file @ 86037742
...@@ -201,5 +201,5 @@ int gm200_sor_new(struct nvkm_disp *, int); ...@@ -201,5 +201,5 @@ int gm200_sor_new(struct nvkm_disp *, int);
int gv100_sor_cnt(struct nvkm_disp *, unsigned long *); int gv100_sor_cnt(struct nvkm_disp *, unsigned long *);
int gv100_sor_new(struct nvkm_disp *, int); int gv100_sor_new(struct nvkm_disp *, int);
int tu104_sor_new(struct nvkm_disp *, int); int tu102_sor_new(struct nvkm_disp *, int);
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View file @ 86037742
...@@ -37,5 +37,5 @@ extern const struct nvkm_disp_oclass gm200_disp_root_oclass; ...@@ -37,5 +37,5 @@ extern const struct nvkm_disp_oclass gm200_disp_root_oclass;
extern const struct nvkm_disp_oclass gp100_disp_root_oclass; extern const struct nvkm_disp_oclass gp100_disp_root_oclass;
extern const struct nvkm_disp_oclass gp102_disp_root_oclass; extern const struct nvkm_disp_oclass gp102_disp_root_oclass;
extern const struct nvkm_disp_oclass gv100_disp_root_oclass; extern const struct nvkm_disp_oclass gv100_disp_root_oclass;
extern const struct nvkm_disp_oclass tu104_disp_root_oclass; extern const struct nvkm_disp_oclass tu102_disp_root_oclass;
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu104.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/roottu102.c
View file @ 86037742
...@@ -25,28 +25,28 @@ ...@@ -25,28 +25,28 @@
#include <nvif/class.h> #include <nvif/class.h>
static const struct nv50_disp_root_func static const struct nv50_disp_root_func
tu104_disp_root = { tu102_disp_root = {
.user = { .user = {
{{0,0,TU104_DISP_CURSOR }, gv100_disp_curs_new }, {{0,0,TU102_DISP_CURSOR }, gv100_disp_curs_new },
{{0,0,TU104_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new }, {{0,0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
{{0,0,TU104_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new }, {{0,0,TU102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
{{0,0,TU104_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new }, {{0,0,TU102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
{} {}
}, },
}; };
static int static int
tu104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, tu102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject) void *data, u32 size, struct nvkm_object **pobject)
{ {
return nv50_disp_root_new_(&tu104_disp_root, disp, oclass, return nv50_disp_root_new_(&tu102_disp_root, disp, oclass,
data, size, pobject); data, size, pobject);
} }
const struct nvkm_disp_oclass const struct nvkm_disp_oclass
tu104_disp_root_oclass = { tu102_disp_root_oclass = {
.base.oclass = TU104_DISP, .base.oclass = TU102_DISP,
.base.minver = -1, .base.minver = -1,
.base.maxver = -1, .base.maxver = -1,
.ctor = tu104_disp_root_new, .ctor = tu102_disp_root_new,
}; };
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu104.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c
View file @ 86037742
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <subdev/timer.h> #include <subdev/timer.h>
static void static void
tu104_sor_dp_vcpi(struct nvkm_ior *sor, int head, tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
u8 slot, u8 slot_nr, u16 pbn, u16 aligned) u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
{ {
struct nvkm_device *device = sor->disp->engine.subdev.device; struct nvkm_device *device = sor->disp->engine.subdev.device;
...@@ -35,7 +35,7 @@ tu104_sor_dp_vcpi(struct nvkm_ior *sor, int head, ...@@ -35,7 +35,7 @@ tu104_sor_dp_vcpi(struct nvkm_ior *sor, int head,
} }
static int static int
tu104_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
{ {
struct nvkm_device *device = sor->disp->engine.subdev.device; struct nvkm_device *device = sor->disp->engine.subdev.device;
const u32 soff = nv50_ior_base(sor); const u32 soff = nv50_ior_base(sor);
...@@ -62,7 +62,7 @@ tu104_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) ...@@ -62,7 +62,7 @@ tu104_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
} }
static const struct nvkm_ior_func static const struct nvkm_ior_func
tu104_sor = { tu102_sor = {
.route = { .route = {
.get = gm200_sor_route_get, .get = gm200_sor_route_get,
.set = gm200_sor_route_set, .set = gm200_sor_route_set,
...@@ -75,11 +75,11 @@ tu104_sor = { ...@@ -75,11 +75,11 @@ tu104_sor = {
}, },
.dp = { .dp = {
.lanes = { 0, 1, 2, 3 }, .lanes = { 0, 1, 2, 3 },
.links = tu104_sor_dp_links, .links = tu102_sor_dp_links,
.power = g94_sor_dp_power, .power = g94_sor_dp_power,
.pattern = gm107_sor_dp_pattern, .pattern = gm107_sor_dp_pattern,
.drive = gm200_sor_dp_drive, .drive = gm200_sor_dp_drive,
.vcpi = tu104_sor_dp_vcpi, .vcpi = tu102_sor_dp_vcpi,
.audio = gv100_sor_dp_audio, .audio = gv100_sor_dp_audio,
.audio_sym = gv100_sor_dp_audio_sym, .audio_sym = gv100_sor_dp_audio_sym,
.watermark = gv100_sor_dp_watermark, .watermark = gv100_sor_dp_watermark,
...@@ -91,7 +91,7 @@ tu104_sor = { ...@@ -91,7 +91,7 @@ tu104_sor = {
}; };
int int
tu104_sor_new(struct nvkm_disp *disp, int id) tu102_sor_new(struct nvkm_disp *disp, int id)
{ {
return nvkm_ior_new_(&tu104_sor, disp, SOR, id); return nvkm_ior_new_(&tu102_sor, disp, SOR, id);
} }
drivers/gpu/drm/nouveau/nvkm/engine/disp/tu104.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
View file @ 86037742
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#include <subdev/timer.h> #include <subdev/timer.h>
static int static int
tu104_disp_init(struct nv50_disp *disp) tu102_disp_init(struct nv50_disp *disp)
{ {
struct nvkm_device *device = disp->base.engine.subdev.device; struct nvkm_device *device = disp->base.engine.subdev.device;
struct nvkm_head *head; struct nvkm_head *head;
...@@ -132,21 +132,21 @@ tu104_disp_init(struct nv50_disp *disp) ...@@ -132,21 +132,21 @@ tu104_disp_init(struct nv50_disp *disp)
} }
static const struct nv50_disp_func static const struct nv50_disp_func
tu104_disp = { tu102_disp = {
.init = tu104_disp_init, .init = tu102_disp_init,
.fini = gv100_disp_fini, .fini = gv100_disp_fini,
.intr = gv100_disp_intr, .intr = gv100_disp_intr,
.uevent = &gv100_disp_chan_uevent, .uevent = &gv100_disp_chan_uevent,
.super = gv100_disp_super, .super = gv100_disp_super,
.root = &tu104_disp_root_oclass, .root = &tu102_disp_root_oclass,
.wndw = { .cnt = gv100_disp_wndw_cnt }, .wndw = { .cnt = gv100_disp_wndw_cnt },
.head = { .cnt = gv100_head_cnt, .new = gv100_head_new }, .head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
.sor = { .cnt = gv100_sor_cnt, .new = tu104_sor_new }, .sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
.ramht_size = 0x2000, .ramht_size = 0x2000,
}; };
int int
tu104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp) tu102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{ {
return nv50_disp_new_(&tu104_disp, device, index, pdisp); return nv50_disp_new_(&tu102_disp, device, index, pdisp);
} }
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