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Commit 8f33e3a0 authored by James Bottomley's avatar James Bottomley
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Merge by Hand

parents afcab5c2 3da9cf28
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Showing with 9002 additions and 8229 deletions
CREDITS
View file @ 8f33e3a0
......@@ -2779,6 +2779,10 @@ N: Christopher Smith
E: x@xman.org
D: Tulip net driver hacker
N: Mark Smith
E: mark.smith@comdev.cc
D: Multicast support in bonding driver
N: Miquel van Smoorenburg
E: miquels@cistron.nl
D: Kernel and net hacker. Sysvinit, minicom. doing Debian stuff.
......
Documentation/DocBook/Makefile
View file @ 8f33e3a0
......@@ -161,18 +161,20 @@ LOG := $(patsubst %.sgml, %.log, $(BOOKS))
OUT := $(patsubst %.sgml, %.out, $(BOOKS))
clean:
rm -f core *~
rm -f $(BOOKS)
rm -f $(DVI) $(AUX) $(TEX) $(LOG) $(OUT)
rm -f $(PNG-parportbook) $(EPS-parportbook)
rm -f $(C-procfs-example)
mrproper: clean
rm -f $(PS) $(PDF)
rm -f -r $(HTML)
rm -f .depend
rm -f $(TOPDIR)/scripts/mkdep-docbook
rm -rf DBTOHTML_OUTPUT*
@echo 'Cleaning up (DocBook)'
@rm -f core *~
@rm -f $(BOOKS)
@rm -f $(DVI) $(AUX) $(TEX) $(LOG) $(OUT)
@rm -f $(PNG-parportbook) $(EPS-parportbook)
@rm -f $(C-procfs-example)
mrproper:
@echo 'Making mrproper (DocBook)'
@rm -f $(PS) $(PDF)
@rm -f -r $(HTML)
@rm -f .depend
@rm -f $(TOPDIR)/scripts/mkdep-docbook
@rm -rf DBTOHTML_OUTPUT*
%.ps : %.sgml
@(which db2ps > /dev/null 2>&1) || \
......
Documentation/filesystems/Locking
View file @ 8f33e3a0
......@@ -88,6 +88,7 @@ prototypes:
void (*read_inode) (struct inode *);
void (*write_inode) (struct inode *, int);
void (*put_inode) (struct inode *);
void (*drop_inode) (struct inode *);
void (*delete_inode) (struct inode *);
void (*put_super) (struct super_block *);
void (*write_super) (struct super_block *);
......@@ -102,6 +103,7 @@ locking rules:
read_inode: yes (see below)
write_inode: no
put_inode: no
drop_inode: no !!!inode_lock!!!
delete_inode: no
clear_inode: no
put_super: yes yes maybe (see below)
......
Documentation/filesystems/ntfs.txt
View file @ 8f33e3a0
......@@ -73,52 +73,27 @@ sloppy=<BOOL> If sloppy is specified, ignore unknown mount options.
Otherwise the default behaviour is to abort mount if
any unknown options are found.
posix=<bool> Deprecated option. Still supported but please use
show_inodes=posix in the future. See description for
show_inodes=opt.
show_sys_files=<bool> Deprecated option. Still supported but please use
show_inodes=system in the future. See description for
show_inodes=opt.
show_inodes=opt Allows choice of which types of inode names readdir()
returns, i.e. this affects what "ls" shows. Following
values can be used for "opt":
system: show system files
win32: long file names (includes POSIX) [DEFAULT]
long: same as win32
dos: short file names only (excludes POSIX)
short: same as dos
posix: same as both win32 and dos
all: all file names
Note that the options are additive, i.e. specifying:
show_inodes=system,show_inodes=win32,show_inodes=dos
is the same as specifying:
show_inodes=all
Note that the "posix" and "all" options will show all
directory names, BUT the link count on each directory
inode entry is set to 1, due to Linux not supporting
directory hard links. This may well confuse some
user space applications, since the directory names will
have the same inode numbers. Thus it is NOT advisable
to use the "posix" and "all" options. We provide them
only for completeness sake.
Further, note that the "system" option will not show
"$MFT" due to bugs/mis-features in glibc. Even though
it does not show, you can specifically "ls" it:
ls -l \$MFT
And of course you can stat it, too.
Further, note that irrespective of what show_inodes
option(s) you use, all files are accessible when you
specify the correct name, even though they may not be
shown in a normal "ls", i.e. you can always access the
system files and both the short and long file names of
files and directories.
Finally, note that win32 and dos file names are not
case sensitive and can be accessed using any
combination of lower and upper case, while POSIX file
names are case sensitive and they can only be accessed
given the correct case.
show_sys_files=<BOOL> If show_sys_files is specified, show the system files
in directory listings. Otherwise the default behaviour
is to hide the system files.
Note that even when show_sys_files is specified, "$MFT"
will not be visible due to bugs/mis-features in glibc.
Further, note that irrespective of show_sys_files, all
files are accessible by name, i.e. you can always do
"ls -l \$UpCase" for example to specifically show the
system file containing the Unicode upcase table.
case_sensitive=<BOOL> If case_sensitive is specified, treat all file names as
case sensitive and create file names in the POSIX
namespace. Otherwise the default behaviour is to treat
file names as case insensitive and to create file names
in the WIN32/LONG name space. Note, the Linux NTFS
driver will never create short file names and will
remove them on rename/delete of the corresponding long
file name.
Note that files remain accessible via their short file
name, if it exists. If case_sensitive, you will need to
provide the correct case of the short file name.
errors=opt What to do when critical file system errors are found.
Following values can be used for "opt":
......@@ -174,12 +149,22 @@ Features
(from 9:43 minutes on average down to 7:53). The time spent in user space
was unchanged but the time spent in the kernel was decreased by a factor of
2.5 (from 85 CPU seconds down to 33).
- The driver does not support short file names in general. For backwards
compatibility, we implement access to files using their short file names if
they exist. The driver will not create short file names however, and a rename
will discard any existing short file name.
Known bugs and (mis-)features
=============================
- None
- The link count on each directory inode entry is set to 1, due to Linux not
supporting directory hard links. This may well confuse some user space
applications, since the directory names will have the same inode numbers.
This also speeds up ntfs_read_inode() immensely. And we haven't found any
problems with this approach so far. If you find a problem with this, please
let us know.
Please send bug reports/comments/feedback/abuse to the Linux-NTFS development
list at sourceforge: linux-ntfs-dev@lists.sourceforge.net
......@@ -260,8 +245,20 @@ number of sectors BEFORE attempting to use it. You have been warned!
ChangeLog
=========
Note that a technical ChangeLog aimed at kernel hackers is in fs/ntfs/ChangeLog.
Note, a technical ChangeLog aimed at kernel hackers is in fs/ntfs/ChangeLog.
2.0.8:
- Remove now obsolete show_inodes and posix mount option(s).
- Restore show_sys_files mount option.
- Add new mount option case_sensitive, to determine if the driver
treats file names as case sensitive or not.
- Mostly drop support for short file names (for backwards compatibility
we only support accessing files via their short file name if one
exists).
- Fix dcache aliasing issues wrt short/long file names.
- Cleanups and minor fixes.
2.0.7:
- Just cleanups.
2.0.6:
- Major bugfix to make compatible with other kernel changes. This fixes
the hangs/oopses on umount.
......
Documentation/filesystems/vfs.txt
View file @ 8f33e3a0
......@@ -178,6 +178,7 @@ struct super_operations {
void (*read_inode) (struct inode *);
void (*write_inode) (struct inode *, int);
void (*put_inode) (struct inode *);
void (*drop_inode) (struct inode *);
void (*delete_inode) (struct inode *);
int (*notify_change) (struct dentry *, struct iattr *);
void (*put_super) (struct super_block *);
......@@ -204,6 +205,19 @@ or bottom half).
put_inode: called when the VFS inode is removed from the inode
cache. This method is optional
drop_inode: called when the last access to the inode is dropped,
with the inode_lock spinlock held.
This method should be either NULL (normal unix filesystem
semantics) or "generic_delete_inode" (for filesystems that do not
want to cache inodes - causing "delete_inode" to always be
called regardless of the value of i_nlink)
The "generic_delete_inode()" behaviour is equivalent to the
old practice of using "force_delete" in the put_inode() case,
but does not have the races that the "force_delete()" approach
had.
delete_inode: called when the VFS wants to delete an inode
notify_change: called when VFS inode attributes are changed. If this
......
MAINTAINERS
View file @ 8f33e3a0
......@@ -1388,6 +1388,14 @@ M: emoenke@gwdg.de
L: linux-kernel@vger.kernel.org
S: Maintained
SCHEDULER
P: Ingo Molnar
M: mingo@elte.hu
P: Robert Love
M: rml@tech9.net
L: linux-kernel@vger.kernel.org
S: Maintained
SCSI CDROM DRIVER
P: Jens Axboe
M: axboe@suse.de
......
Makefile
View file @ 8f33e3a0
This diff is collapsed.
Rules.make
View file @ 8f33e3a0
This diff is collapsed.
arch/alpha/kernel/osf_sys.c
View file @ 8f33e3a0
......@@ -116,15 +116,17 @@ static int osf_filldir(void *__buf, const char *name, int namlen, loff_t offset,
if (reclen > buf->count)
return -EINVAL;
if (buf->basep) {
put_user(offset, buf->basep);
if (put_user(offset, buf->basep))
return -EFAULT;
buf->basep = NULL;
}
dirent = buf->dirent;
put_user(ino, &dirent->d_ino);
put_user(namlen, &dirent->d_namlen);
put_user(reclen, &dirent->d_reclen);
copy_to_user(dirent->d_name, name, namlen);
put_user(0, dirent->d_name + namlen);
if (copy_to_user(dirent->d_name, name, namlen) ||
put_user(0, dirent->d_name + namlen))
return -EFAULT;
((char *) dirent) += reclen;
buf->dirent = dirent;
buf->count -= reclen;
......@@ -629,18 +631,16 @@ asmlinkage long osf_proplist_syscall(enum pl_code code, union pl_args *args)
error = args->fset.nbytes;
break;
case PL_GET:
get_user(min_buf_size_ptr, &args->get.min_buf_size);
error = verify_area(VERIFY_WRITE, min_buf_size_ptr,
sizeof(*min_buf_size_ptr));
if (!error)
put_user(0, min_buf_size_ptr);
error = get_user(min_buf_size_ptr, &args->get.min_buf_size);
if (error)
break;
error = put_user(0, min_buf_size_ptr);
break;
case PL_FGET:
get_user(min_buf_size_ptr, &args->fget.min_buf_size);
error = verify_area(VERIFY_WRITE, min_buf_size_ptr,
sizeof(*min_buf_size_ptr));
if (!error)
put_user(0, min_buf_size_ptr);
error = get_user(min_buf_size_ptr, &args->fget.min_buf_size);
if (error)
break;
error = put_user(0, min_buf_size_ptr);
break;
case PL_DEL:
case PL_FDEL:
......
arch/alpha/kernel/signal.c
View file @ 8f33e3a0
......@@ -253,9 +253,8 @@ restore_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
struct switch_stack *sw)
{
unsigned long usp;
long i, err = 0;
long i, err = __get_user(regs->pc, &sc->sc_pc);
err |= __get_user(regs->pc, &sc->sc_pc);
sw->r26 = (unsigned long) ret_from_sys_call;
err |= __get_user(regs->r0, sc->sc_regs+0);
......
arch/arm/Makefile
View file @ 8f33e3a0
......@@ -201,15 +201,30 @@ MAKETOOLS =$(MAKE) -C arch/$(ARCH)/tools
$(patsubst %,_dir_%, $(SUBDIRS)): maketools
$(patsubst %,_modsubdir_%,$(MOD_DIRS)): maketools
symlinks: archsymlinks
# Update machine arch and proc symlinks if something which affects
# them changed. We use .arch and .proc to indicate when they were
# updated last, otherwise make uses the target directory mtime.
archsymlinks:
$(RM) include/asm-arm/arch include/asm-arm/proc
(cd include/asm-arm; ln -sf arch-$(INCDIR) arch; ln -sf proc-$(PROCESSOR) proc)
include/asm-arm/.arch: $(wildcard include/config/arch/*.h)
@echo 'Making asm-arm/arch -> asm-arm/arch-$(INCDIR) symlink'
@rm -f include/asm-arm/arch
@ln -sf arch-$(INCDIR) include/asm-arm/arch
@touch $@
include/asm-arm/.proc: $(wildcard include/config/cpu/32.h) $(wildcard include/config/cpu/26.h)
@echo 'Making asm-arm/proc -> asm-arm/proc-$(PROCESSOR) symlink'
@rm -f include/asm-arm/proc
@ln -sf proc-$(PROCESSOR) include/asm-arm/proc
@touch $@
.hdepend: include/asm-arm/.arch include/asm-arm/.proc
vmlinux: arch/arm/vmlinux.lds
arch/arm/vmlinux.lds: $(LDSCRIPT) FORCE
arch/arm/vmlinux.lds: arch/arm/Makefile $(LDSCRIPT) \
$(wildcard include/config/cpu/32.h) \
$(wildcard include/config/cpu/26.h) \
$(wildcard include/config/arch/*.h)
@sed 's/TEXTADDR/$(TEXTADDR)/;s/DATAADDR/$(DATAADDR)/' $(LDSCRIPT) >$@
bzImage zImage zinstall Image bootpImage install: vmlinux
......@@ -220,39 +235,26 @@ CLEAN_FILES += \
MRPROPER_FILES += \
arch/arm/tools/constants.h* \
include/asm-arm/arch \
include/asm-arm/proc \
include/asm-arm/arch include/asm-arm/.arch \
include/asm-arm/proc include/asm-arm/.proc \
include/asm-arm/constants.h* \
include/asm-arm/mach-types.h
# We use MRPROPER_FILES and CLEAN_FILES now
archmrproper:
archmrproper: FORCE
@/bin/true
archclean:
archclean: FORCE
@$(MAKEBOOT) clean
archdep: scripts/mkdep archsymlinks
archdep: FORCE
@$(MAKETOOLS) dep
@$(MAKEBOOT) dep
# we need version.h
maketools: checkbin include/linux/version.h
maketools: include/linux/version.h FORCE
@$(MAKETOOLS) all
# Ensure this is ld "2.9.4" or later
NEW_LINKER := $(shell $(LD) --gc-sections --version >/dev/null 2>&1; echo $$?)
ifneq ($(NEW_LINKER),0)
checkbin:
@echo '*** ${VERSION}.${PATCHLEVEL} kernels no longer build correctly with old versions of binutils.'
@echo '*** Please upgrade your binutils to 2.9.5.'
@false
else
checkbin:
@true
endif
# My testing targets (that short circuit a few dependencies)
zImg:; @$(MAKEBOOT) zImage
Img:; @$(MAKEBOOT) Image
......
arch/arm/boot/Makefile
View file @ 8f33e3a0
......@@ -114,12 +114,12 @@ endif
export SYSTEM ZTEXTADDR ZBSSADDR ZRELADDR INITRD_PHYS PARAMS_PHYS
Image: $(CONFIGURE) $(SYSTEM)
Image: $(SYSTEM)
$(OBJCOPY) -O binary -R .note -R .comment -S $(SYSTEM) $@
bzImage: zImage
zImage: $(CONFIGURE) compressed/vmlinux
zImage: compressed/vmlinux
$(OBJCOPY) -O binary -R .note -R .comment -S compressed/vmlinux $@
bootpImage: bootp/bootp
......@@ -135,10 +135,10 @@ initrd:
@test "$(INITRD_PHYS)" != "" || (echo This architecture does not support INITRD; exit -1)
@test "$(INITRD)" != "" || (echo You must specify INITRD; exit -1)
install: $(CONFIGURE) Image
install: Image
sh ./install.sh $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) Image $(TOPDIR)/System.map "$(INSTALL_PATH)"
zinstall: $(CONFIGURE) zImage
zinstall: zImage
sh ./install.sh $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) zImage $(TOPDIR)/System.map "$(INSTALL_PATH)"
clean:
......
arch/arm/mach-adifcc/mm.c
View file @ 8f33e3a0
/*
* linux/arch/arm/mach-xscale/mm.c
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -14,11 +14,10 @@
static struct map_desc adifcc_io_desc[] __initdata = {
/* on-board devices */
{ 0xff400000, 0x00400000, 0x00300000, DOMAIN_IO, 0, 1, 0, 0},
LAST_DESC
{ 0xff400000, 0x00400000, 0x00300000, MT_DEVICE }
};
void __init adifcc_map_io(void)
{
iotable_init(adifcc_io_desc);
iotable_init(adifcc_io_desc, ARRAY_SIZE(adifcc_io_desc));
}
arch/arm/mach-anakin/mm.c
View file @ 8f33e3a0
......@@ -10,8 +10,7 @@
* Changelog:
* 09-Apr-2001 W/TTC Created
*/
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/io.h>
......@@ -19,14 +18,13 @@
#include <asm/mach/map.h>
static struct map_desc anakin_io_desc[] __initdata = {
{ IO_BASE, IO_START, IO_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ FLASH_BASE, FLASH_START, FLASH_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ VGA_BASE, VGA_START, VGA_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ IO_BASE, IO_START, IO_SIZE, MT_DEVICE },
{ FLASH_BASE, FLASH_START, FLASH_SIZE, MT_DEVICE },
{ VGA_BASE, VGA_START, VGA_SIZE, MT_DEVICE }
};
void __init
anakin_map_io(void)
{
iotable_init(anakin_io_desc);
iotable_init(anakin_io_desc, ARRAY_SIZE(anakin_io_desc));
}
arch/arm/mach-clps711x/autcpu12.c
View file @ 8f33e3a0
......@@ -17,6 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
......@@ -48,18 +49,16 @@ extern void clps711x_init_irq(void);
*/
static struct map_desc autcpu12_io_desc[] __initdata = {
/* virtual, physical, length, domain, r, w, c, b */
/* virtual, physical, length, type */
/* memory-mapped extra io and CS8900A Ethernet chip */
/* ethernet chip */
{ AUTCPU12_VIRT_CS8900A, AUTCPU12_PHYS_CS8900A, SZ_1M, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ AUTCPU12_VIRT_CS8900A, AUTCPU12_PHYS_CS8900A, SZ_1M, MT_DEVICE }
};
void __init autcpu12_map_io(void)
{
clps711x_map_io();
iotable_init(autcpu12_io_desc);
iotable_init(autcpu12_io_desc, ARRAY_SIZE(autcpu12_io_desc));
}
MACHINE_START(AUTCPU12, "autronix autcpu12")
......
arch/arm/mach-clps711x/cdb89712.c
View file @ 8f33e3a0
......@@ -17,6 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
......@@ -40,14 +41,13 @@ extern void clps711x_map_io(void);
* ethernet driver, perhaps.
*/
static struct map_desc cdb89712_io_desc[] __initdata = {
{ ETHER_BASE, ETHER_START, ETHER_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ ETHER_BASE, ETHER_START, ETHER_SIZE, MT_DEVICE }
};
static void __init cdb89712_map_io(void)
{
clps711x_map_io();
iotable_init(cdb89712_io_desc);
iotable_init(cdb89712_io_desc, ARRAY_SIZE(cdb89712_io_desc));
}
MACHINE_START(CDB89712, "Cirrus-CDB89712")
......
arch/arm/mach-clps711x/edb7211-mm.c
View file @ 8f33e3a0
......@@ -19,13 +19,12 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
......@@ -52,22 +51,20 @@ extern void clps711x_map_io(void);
* happens).
*/
static struct map_desc edb7211_io_desc[] __initdata = {
/* virtual, physical, length, domain, r, w, c, b */
/* virtual, physical, length, type */
/* memory-mapped extra keyboard row and CS8900A Ethernet chip */
{ EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, SZ_1M, DOMAIN_IO, 0, 1, 0, 0 },
{ EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, SZ_1M, DOMAIN_IO, 0, 1, 0, 0 },
{ EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, SZ_1M, MT_DEVICE },
{ EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, SZ_1M, MT_DEVICE },
/* flash banks */
{ EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, SZ_8M, DOMAIN_KERNEL, 0, 1, 0, 0 },
{ EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, SZ_8M, DOMAIN_KERNEL, 0, 1, 0, 0 },
LAST_DESC
{ EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, SZ_8M, MT_DEVICE },
{ EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, SZ_8M, MT_DEVICE }
};
void __init edb7211_map_io(void)
{
clps711x_map_io();
iotable_init(edb7211_io_desc);
iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
}
arch/arm/mach-clps711x/mm.c
View file @ 8f33e3a0
......@@ -19,6 +19,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -31,40 +32,14 @@
#include <asm/mach/map.h>
#include <asm/hardware/clps7111.h>
#if 0 //def CONFIG_DISCONTIGMEM
/*
* The assumption of maximum 4 discontiguous memory banks is present
* in several places in the ARM kernel, including the parameter block
* (this affects boot loaders, too). Banks do not necessarily
* correspond 1:1 with NUMA nodes, although they usually will,
* especially if they are widely discontiguous.
*
* - note that the parameter block is depreciated for new implementations
* - also note that discontig_node_data is actually used
* -- rmk
*/
static bootmem_data_t node_bootmem_data[4];
pg_data_t clps711x_node_data[4] = {
{ bdata: &node_bootmem_data[0] },
{ bdata: &node_bootmem_data[1] },
{ bdata: &node_bootmem_data[2] },
{ bdata: &node_bootmem_data[3] },
};
#endif
/*
* This maps the generic CLPS711x registers
*/
static struct map_desc clps711x_io_desc[] __initdata = {
{ CLPS7111_VIRT_BASE, CLPS7111_PHYS_BASE, 1048576, DOMAIN_IO, 0, 1 },
LAST_DESC
{ CLPS7111_VIRT_BASE, CLPS7111_PHYS_BASE, 1048576, MT_DEVICE }
};
void __init clps711x_map_io(void)
{
iotable_init(clps711x_io_desc);
iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
}
arch/arm/mach-clps711x/p720t.c
View file @ 8f33e3a0
......@@ -18,6 +18,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/string.h>
......@@ -43,9 +44,8 @@ extern void clps711x_map_io(void);
* We map both here.
*/
static struct map_desc p720t_io_desc[] __initdata = {
{ SYSPLD_VIRT_BASE, SYSPLD_PHYS_BASE, 1048576, DOMAIN_IO, 0, 1 },
{ 0xfe400000, 0x10400000, 1048576, DOMAIN_IO, 0, 1 },
LAST_DESC
{ SYSPLD_VIRT_BASE, SYSPLD_PHYS_BASE, 1048576, MT_DEVICE },
{ 0xfe400000, 0x10400000, 1048576, MT_DEVICE }
};
static void __init
......@@ -77,7 +77,7 @@ fixup_p720t(struct machine_desc *desc, struct tag *tag,
static void __init p720t_map_io(void)
{
clps711x_map_io();
iotable_init(p720t_io_desc);
iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
}
MACHINE_START(P720T, "ARM-Prospector720T")
......
arch/arm/mach-clps7500/core.c
View file @ 8f33e3a0
/*
* linux/arch/arm/mm/mm-cl7500.c
* linux/arch/arm/mach-clps7500/core.c
*
* Copyright (C) 1998 Russell King
* Copyright (C) 1999 Nexus Electronics Ltd
*
* Extra MM routines for CL7500 architecture
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
......@@ -215,16 +216,15 @@ static void __init clps7500_init_irq(void)
}
static struct map_desc cl7500_io_desc[] __initdata = {
{ IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1 }, /* IO space */
{ ISA_BASE, ISA_START, ISA_SIZE , DOMAIN_IO, 0, 1 }, /* ISA space */
{ FLASH_BASE, FLASH_START, FLASH_SIZE, DOMAIN_IO, 0, 1 }, /* Flash */
{ LED_BASE, LED_START, LED_SIZE , DOMAIN_IO, 0, 1 }, /* LED */
LAST_DESC
{ IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, /* IO space */
{ ISA_BASE, ISA_START, ISA_SIZE, MT_DEVICE }, /* ISA space */
{ FLASH_BASE, FLASH_START, FLASH_SIZE, MT_DEVICE }, /* Flash */
{ LED_BASE, LED_START, LED_SIZE, MT_DEVICE } /* LED */
};
static void __init clps7500_map_io(void)
{
iotable_init(cl7500_io_desc);
iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
}
MACHINE_START(CLPS7500, "CL-PS7500")
......
arch/arm/mach-ebsa110/core.c
View file @ 8f33e3a0
......@@ -9,6 +9,7 @@
*
* Extra MM routines for the EBSA-110 architecture
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -71,22 +72,21 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
/*
* sparse external-decode ISAIO space
*/
{ IRQ_STAT, TRICK4_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_STAT/IRQ_MCLR */
{ IRQ_MASK, TRICK3_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_MASK/IRQ_MSET */
{ SOFT_BASE, TRICK1_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* SOFT_BASE */
{ PIT_BASE, TRICK0_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* PIT_BASE */
{ IRQ_STAT, TRICK4_PHYS, PGDIR_SIZE, MT_DEVICE }, /* IRQ_STAT/IRQ_MCLR */
{ IRQ_MASK, TRICK3_PHYS, PGDIR_SIZE, MT_DEVICE }, /* IRQ_MASK/IRQ_MSET */
{ SOFT_BASE, TRICK1_PHYS, PGDIR_SIZE, MT_DEVICE }, /* SOFT_BASE */
{ PIT_BASE, TRICK0_PHYS, PGDIR_SIZE, MT_DEVICE }, /* PIT_BASE */
/*
* self-decode ISAIO space
*/
{ ISAIO_BASE, ISAIO_PHYS, ISAIO_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ ISAMEM_BASE, ISAMEM_PHYS, ISAMEM_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ ISAIO_BASE, ISAIO_PHYS, ISAIO_SIZE, MT_DEVICE },
{ ISAMEM_BASE, ISAMEM_PHYS, ISAMEM_SIZE, MT_DEVICE }
};
static void __init ebsa110_map_io(void)
{
iotable_init(ebsa110_io_desc);
iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
}
MACHINE_START(EBSA110, "EBSA110")
......
arch/arm/mach-epxa10db/mm.c
View file @ 8f33e3a0
......@@ -19,14 +19,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
......@@ -34,16 +31,15 @@
/* Page table mapping for I/O region */
static struct map_desc epxa10db_io_desc[] __initdata = {
{ IO_ADDRESS(EXC_REGISTERS_BASE), EXC_REGISTERS_BASE, SZ_16K , DOMAIN_IO, 0, 1},
{IO_ADDRESS(EXC_PLD_BLOCK0_BASE), EXC_PLD_BLOCK0_BASE, SZ_16K , DOMAIN_IO, 0, 1},
{IO_ADDRESS(EXC_PLD_BLOCK1_BASE), EXC_PLD_BLOCK1_BASE, SZ_16K , DOMAIN_IO, 0, 1},
{IO_ADDRESS(EXC_PLD_BLOCK2_BASE), EXC_PLD_BLOCK2_BASE, SZ_16K , DOMAIN_IO, 0, 1},
{IO_ADDRESS(EXC_PLD_BLOCK3_BASE), EXC_PLD_BLOCK3_BASE, SZ_16K , DOMAIN_IO, 0, 1},
{ FLASH_VADDR(EXC_EBI_BLOCK0_BASE), EXC_EBI_BLOCK0_BASE, SZ_16M , DOMAIN_IO, 0, 1},
LAST_DESC
{ IO_ADDRESS(EXC_REGISTERS_BASE), EXC_REGISTERS_BASE, SZ_16K, MT_DEVICE },
{ IO_ADDRESS(EXC_PLD_BLOCK0_BASE), EXC_PLD_BLOCK0_BASE, SZ_16K, MT_DEVICE },
{ IO_ADDRESS(EXC_PLD_BLOCK1_BASE), EXC_PLD_BLOCK1_BASE, SZ_16K, MT_DEVICE },
{ IO_ADDRESS(EXC_PLD_BLOCK2_BASE), EXC_PLD_BLOCK2_BASE, SZ_16K, MT_DEVICE },
{ IO_ADDRESS(EXC_PLD_BLOCK3_BASE), EXC_PLD_BLOCK3_BASE, SZ_16K, MT_DEVICE },
{ FLASH_VADDR(EXC_EBI_BLOCK0_BASE), EXC_EBI_BLOCK0_BASE, SZ_16M, MT_DEVICE }
};
void __init epxa10db_map_io(void)
{
iotable_init(epxa10db_io_desc);
iotable_init(epxa10db_io_desc, ARRAY_SIZE(epxa10db_io_desc));
}
arch/arm/mach-footbridge/mm.c
View file @ 8f33e3a0
......@@ -10,6 +10,7 @@
* Extra MM routines for the EBSA285 architecture
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -28,9 +29,8 @@
* it means that we have extra bullet protection on our feet.
*/
static struct map_desc fb_common_io_desc[] __initdata = {
{ ARMCSR_BASE, DC21285_ARMCSR_BASE, ARMCSR_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ XBUS_BASE, 0x40000000, XBUS_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ ARMCSR_BASE, DC21285_ARMCSR_BASE, ARMCSR_SIZE, MT_DEVICE },
{ XBUS_BASE, 0x40000000, XBUS_SIZE, MT_DEVICE }
};
/*
......@@ -39,13 +39,12 @@ static struct map_desc fb_common_io_desc[] __initdata = {
*/
static struct map_desc ebsa285_host_io_desc[] __initdata = {
#if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
{ PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCICFG0_BASE, DC21285_PCI_TYPE_0_CONFIG, PCICFG0_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCICFG1_BASE, DC21285_PCI_TYPE_1_CONFIG, PCICFG1_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIIACK_BASE, DC21285_PCI_IACK, PCIIACK_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, MT_DEVICE },
{ PCICFG0_BASE, DC21285_PCI_TYPE_0_CONFIG, PCICFG0_SIZE, MT_DEVICE },
{ PCICFG1_BASE, DC21285_PCI_TYPE_1_CONFIG, PCICFG1_SIZE, MT_DEVICE },
{ PCIIACK_BASE, DC21285_PCI_IACK, PCIIACK_SIZE, MT_DEVICE },
{ PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, MT_DEVICE }
#endif
LAST_DESC
};
/*
......@@ -53,33 +52,27 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
*/
static struct map_desc co285_io_desc[] __initdata = {
#ifdef CONFIG_ARCH_CO285
{ PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIO_BASE, DC21285_PCI_IO, PCIO_SIZE, MT_DEVICE },
{ PCIMEM_BASE, DC21285_PCI_MEM, PCIMEM_SIZE, MT_DEVICE }
#endif
LAST_DESC
};
void __init footbridge_map_io(void)
{
struct map_desc *desc = NULL;
/*
* Set up the common mapping first; we need this to
* determine whether we're in host mode or not.
*/
iotable_init(fb_common_io_desc);
iotable_init(fb_common_io_desc, ARRAY_SIZE(fb_common_io_desc));
/*
* Now, work out what we've got to map in addition on this
* platform.
*/
if (machine_is_co285())
desc = co285_io_desc;
else if (footbridge_cfn_mode())
desc = ebsa285_host_io_desc;
if (desc)
iotable_init(desc);
iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
if (footbridge_cfn_mode())
iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
}
#ifdef CONFIG_FOOTBRIDGE_ADDIN
......
arch/arm/mach-ftvpci/core.c
View file @ 8f33e3a0
......@@ -8,6 +8,7 @@
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -76,17 +77,16 @@ static void __init ftvpci_init_irq(void)
}
static struct map_desc ftvpci_io_desc[] __initdata = {
{ INTCONT_BASE, INTCONT_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 },
{ PLX_BASE, PLX_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 },
{ PCIO_BASE, PLX_IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 },
{ DUART_BASE, DUART_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 },
{ STATUS_BASE, STATUS_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ INTCONT_BASE, INTCONT_START, 0x00001000, MT_DEVICE },
{ PLX_BASE, PLX_START, 0x00001000, MT_DEVICE },
{ PCIO_BASE, PLX_IO_START, 0x00100000, MT_DEVICE },
{ DUART_BASE, DUART_START, 0x00001000, MT_DEVICE },
{ STATUS_BASE, STATUS_START, 0x00001000, MT_DEVICE }
};
static void __init ftvpci_map_io(void)
{
iotable_init(ftvpci_io_desc);
iotable_init(ftvpci_io_desc, ARRAY_SIZE(ftvpci_io_desc));
}
MACHINE_START(NEXUSPCI, "FTV/PCI")
......
arch/arm/mach-integrator/mm.c
View file @ 8f33e3a0
......@@ -20,14 +20,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
......@@ -53,26 +50,25 @@
*/
static struct map_desc integrator_io_desc[] __initdata = {
{ IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_RTC_BASE), INTEGRATOR_RTC_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_KBD_BASE), INTEGRATOR_KBD_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_MOUSE_BASE), INTEGRATOR_MOUSE_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K , DOMAIN_IO, 0, 1},
{ PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M , DOMAIN_IO, 0, 1},
{ PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M , DOMAIN_IO, 0, 1},
{ PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_64K , DOMAIN_IO, 0, 1},
{ PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K , DOMAIN_IO, 0, 1},
LAST_DESC
{ IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_RTC_BASE), INTEGRATOR_RTC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_KBD_BASE), INTEGRATOR_KBD_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_MOUSE_BASE), INTEGRATOR_MOUSE_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
{ PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M, MT_DEVICE },
{ PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M, MT_DEVICE },
{ PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_64K, MT_DEVICE },
{ PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K, MT_DEVICE }
};
void __init integrator_map_io(void)
{
iotable_init(integrator_io_desc);
iotable_init(integrator_io_desc, ARRAY_SIZE(integrator_io_desc));
}
arch/arm/mach-iop310/mm.c
View file @ 8f33e3a0
......@@ -14,6 +14,7 @@
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -32,17 +33,16 @@
* Standard IO mapping for all IOP310 based systems
*/
static struct map_desc iop80310_std_desc[] __initdata = {
/* virtual physical length domain r w c b */
/* virtual physical length type */
// IOP310 Memory Mapped Registers
{ 0xe8001000, 0x00001000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 },
{ 0xe8001000, 0x00001000, 0x00001000, MT_DEVICE },
// PCI I/O Space
{ 0xfe000000, 0x90000000, 0x00020000, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ 0xfe000000, 0x90000000, 0x00020000, MT_DEVICE }
};
void __init iop310_map_io(void)
{
iotable_init(iop80310_std_desc);
iotable_init(iop80310_std_desc, ARRAY_SIZE(iop80310_std_desc));
}
/*
......@@ -50,10 +50,9 @@ void __init iop310_map_io(void)
*/
#ifdef CONFIG_ARCH_IQ80310
static struct map_desc iq80310_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
/* virtual physical length type */
// IQ80310 On-Board Devices
{ 0xfe800000, 0xfe800000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ 0xfe800000, 0xfe800000, 0x00100000, MT_DEVICE }
};
void __init iq80310_map_io(void)
......@@ -65,7 +64,7 @@ void __init iq80310_map_io(void)
iop310_map_io();
iotable_init(iq80310_io_desc);
iotable_init(iq80310_io_desc, ARRAY_SIZE(iq80310_io_desc));
}
#endif // CONFIG_ARCH_IQ80310
arch/arm/mach-l7200/core.c
View file @ 8f33e3a0
......@@ -6,6 +6,7 @@
* Extra MM routines for L7200 architecture
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
......@@ -69,17 +70,16 @@ static void __init l7200_init_irq(void)
}
static struct map_desc l7200_io_desc[] __initdata = {
{ IO_BASE, IO_START, IO_SIZE, DOMAIN_IO, 0, 1 ,0 ,0},
{ IO_BASE_2, IO_START_2, IO_SIZE_2, DOMAIN_IO, 0, 1 ,0 ,0},
{ AUX_BASE, AUX_START, AUX_SIZE, DOMAIN_IO, 0, 1 ,0 ,0},
{ FLASH1_BASE, FLASH1_START, FLASH1_SIZE, DOMAIN_IO, 0, 1 ,0 ,0},
{ FLASH2_BASE, FLASH2_START, FLASH2_SIZE, DOMAIN_IO, 0, 1 ,0 ,0},
LAST_DESC
{ IO_BASE, IO_START, IO_SIZE, MT_DEVICE },
{ IO_BASE_2, IO_START_2, IO_SIZE_2, MT_DEVICE },
{ AUX_BASE, AUX_START, AUX_SIZE, MT_DEVICE },
{ FLASH1_BASE, FLASH1_START, FLASH1_SIZE, MT_DEVICE },
{ FLASH2_BASE, FLASH2_START, FLASH2_SIZE, MT_DEVICE }
};
static void __init l7200_map_io(void)
{
iotable_init(l7200_io_desc);
iotable_init(l7200_io_desc, ARRAY_SIZE(l7200_io_desc));
}
MACHINE_START(L7200, "LinkUp Systems L7200")
......
arch/arm/mach-pxa/generic.c
View file @ 8f33e3a0
......@@ -88,16 +88,15 @@ EXPORT_SYMBOL(pxa_gpio_mode);
* cache flush area.
*/
static struct map_desc standard_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf6000000, 0x20000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA0 IO */
{ 0xf7000000, 0x30000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCMCIA1 IO */
{ 0xfc000000, 0x40000000, 0x01400000, DOMAIN_IO, 0, 1, 0, 0 }, /* Devs */
{ 0xfe000000, 0x44000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD */
{ 0xff000000, 0x48000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* Mem Ctl */
LAST_DESC
/* virtual physical length type */
{ 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
{ 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
{ 0xfc000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
{ 0xfe000000, 0x44000000, 0x00200000, MT_DEVICE }, /* LCD */
{ 0xff000000, 0x48000000, 0x00200000, MT_DEVICE } /* Mem Ctl */
};
void __init pxa_map_io(void)
{
iotable_init(standard_io_desc);
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}
arch/arm/mach-pxa/idp.c
View file @ 8f33e3a0
......@@ -10,6 +10,7 @@
* 2001-09-13: Cliff Brake <cbrake@accelent.com>
* Initial code
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
......@@ -69,45 +70,38 @@ static void __init idp_init_irq(void)
}
static struct map_desc idp_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
/* virtual physical length type */
#ifndef PXA_IDP_REV02
{ IDP_CTRL_PORT_BASE,
IDP_CTRL_PORT_PHYS,
IDP_CTRL_PORT_SIZE,
DOMAIN_IO,
0, 1, 0, 0 },
MT_DEVICE },
#endif
{ IDP_IDE_BASE,
IDP_IDE_PHYS,
IDP_IDE_SIZE,
DOMAIN_IO,
0, 1, 0, 0 },
MT_DEVICE },
{ IDP_ETH_BASE,
IDP_ETH_PHYS,
IDP_ETH_SIZE,
DOMAIN_IO,
0, 1, 0, 0 },
MT_DEVICE },
{ IDP_COREVOLT_BASE,
IDP_COREVOLT_PHYS,
IDP_COREVOLT_SIZE,
DOMAIN_IO,
0, 1, 0, 0 },
MT_DEVICE },
{ IDP_CPLD_BASE,
IDP_CPLD_PHYS,
IDP_CPLD_SIZE,
DOMAIN_IO,
0, 1, 0, 0 },
LAST_DESC
MT_DEVICE }
};
static void __init idp_map_io(void)
{
pxa_map_io();
iotable_init(idp_io_desc);
iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
set_GPIO_IRQ_edge(IRQ_TO_GPIO_2_80(TOUCH_PANEL_IRQ), TOUCH_PANEL_IRQ_EDGE);
}
......
arch/arm/mach-pxa/lubbock.c
View file @ 8f33e3a0
......@@ -11,6 +11,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/fs.h>
......@@ -120,18 +121,17 @@ static int __init lubbock_init(void)
__initcall(lubbock_init);
static struct map_desc lubbock_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
{ 0xf1000000, 0x0c000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 IO */
{ 0xf1100000, 0x0e000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN91C96 Attr */
{ 0xf4000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x08000000, 0x00100000, MT_DEVICE }, /* CPLD */
{ 0xf1000000, 0x0c000000, 0x00100000, MT_DEVICE }, /* LAN91C96 IO */
{ 0xf1100000, 0x0e000000, 0x00100000, MT_DEVICE }, /* LAN91C96 Attr */
{ 0xf4000000, 0x10000000, 0x00400000, MT_DEVICE } /* SA1111 */
};
static void __init lubbock_map_io(void)
{
pxa_map_io();
iotable_init(lubbock_io_desc);
iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
/* This enables the BTUART */
CKEN |= CKEN7_BTUART;
......
arch/arm/mach-rpc/riscpc.c
View file @ 8f33e3a0
......@@ -9,6 +9,7 @@
*
* Architecture specific fixups.
*/
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/pm.h>
......@@ -61,15 +62,14 @@ __tagtable(ATAG_ACORN, parse_tag_acorn);
#endif
static struct map_desc rpc_io_desc[] __initdata = {
{ SCREEN_BASE, SCREEN_START, 2*1048576, DOMAIN_IO, 0, 1, 0, 0 }, /* VRAM */
{ IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 }, /* IO space */
{ EASI_BASE, EASI_START, EASI_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* EASI space */
LAST_DESC
{ SCREEN_BASE, SCREEN_START, 2*1048576, MT_DEVICE }, /* VRAM */
{ IO_BASE, IO_START, IO_SIZE , MT_DEVICE }, /* IO space */
{ EASI_BASE, EASI_START, EASI_SIZE, MT_DEVICE } /* EASI space */
};
void __init rpc_map_io(void)
{
iotable_init(rpc_io_desc);
iotable_init(rpc_io_desc, ARRAY_SIZE(rpc_io_desc));
/*
* RiscPC can't handle half-word loads and stores
......
arch/arm/mach-sa1100/adsbitsy.c
View file @ 8f33e3a0
......@@ -9,7 +9,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
......@@ -77,9 +77,8 @@ static void __init adsbitsy_init_irq(void)
}
static struct map_desc adsbitsy_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf4000000, 0x18000000, 0x00800000, MT_DEVICE } /* SA1111 */
};
static int adsbitsy_uart_open(struct uart_port *port, struct uart_info *info)
......@@ -106,7 +105,7 @@ static struct sa1100_port_fns adsbitsy_port_fns __initdata = {
static void __init adsbitsy_map_io(void)
{
sa1100_map_io();
iotable_init(adsbitsy_io_desc);
iotable_init(adsbitsy_io_desc, ARRAY_SIZE(adsbitsy_io_desc));
sa1100_register_uart_fns(&adsbitsy_port_fns);
sa1100_register_uart(0, 3);
......
arch/arm/mach-sa1100/assabet.c
View file @ 8f33e3a0
......@@ -171,15 +171,6 @@ fixup_assabet(struct machine_desc *desc, struct tag *tags,
}
static struct map_desc assabet_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf1000000, 0x12000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
{ 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
/* f3000000 - neponset system registers */
/* f4000000 - neponset SA1111 registers */
LAST_DESC
};
static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
{
if (port->mapbase == _Ser1UTCR0) {
......@@ -255,12 +246,18 @@ static struct sa1100_port_fns assabet_port_fns __initdata = {
pm: assabet_uart_pm,
};
static struct map_desc assabet_io_desc[] __initdata = {
/* virtual physical length type */
{ 0xf1000000, 0x12000000, 0x00100000, MT_DEVICE }, /* Board Control Register */
{ 0xf2800000, 0x4b800000, 0x00800000, MT_DEVICE } /* MQ200 */
};
static void __init assabet_map_io(void)
{
extern void neponset_map_io(void);
sa1100_map_io();
iotable_init(assabet_io_desc);
iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
if (machine_has_neponset()) {
#ifdef CONFIG_ASSABET_NEPONSET
......
arch/arm/mach-sa1100/badge4.c
View file @ 8f33e3a0
......@@ -145,17 +145,16 @@ EXPORT_SYMBOL(badge4_set_5V);
static struct map_desc badge4_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{0xf1000000, 0x08000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SRAM bank 1 */
{0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SRAM bank 2 */
{0xf4000000, 0x48000000, 0x00100000, DOMAIN_IO, 0,1,0,0},/* SA-1111 */
LAST_DESC
/* virtual physical length type */
{0xf1000000, 0x08000000, 0x00100000, MT_DEVICE },/* SRAM bank 1 */
{0xf2000000, 0x10000000, 0x00100000, MT_DEVICE },/* SRAM bank 2 */
{0xf4000000, 0x48000000, 0x00100000, MT_DEVICE } /* SA-1111 */
};
static void __init badge4_map_io(void)
{
sa1100_map_io();
iotable_init(badge4_io_desc);
iotable_init(badge4_io_desc, ARRAY_SIZE(badge4_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/cerf.c
View file @ 8f33e3a0
......@@ -36,20 +36,19 @@ static void __init cerf_init_irq(void)
}
static struct map_desc cerf_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Crystal Ethernet Chip */
/* virtual physical length type */
{ 0xf0000000, 0x08000000, 0x00100000, MT_DEVICE } /* Crystal Ethernet Chip */
#ifdef CONFIG_SA1100_CERF_CPLD
{ 0xf1000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD Chip */
{ 0xf2000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CerfPDA Bluetooth */
{ 0xf3000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* CerfPDA Serial */
,{ 0xf1000000, 0x40000000, 0x00100000, MT_DEVICE }, /* CPLD Chip */
{ 0xf2000000, 0x10000000, 0x00100000, MT_DEVICE }, /* CerfPDA Bluetooth */
{ 0xf3000000, 0x18000000, 0x00100000, MT_DEVICE } /* CerfPDA Serial */
#endif
LAST_DESC
};
static void __init cerf_map_io(void)
{
sa1100_map_io();
iotable_init(cerf_io_desc);
iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc));
sa1100_register_uart(0, 3);
#ifdef CONFIG_SA1100_CERF_IRDA_ENABLED
......
arch/arm/mach-sa1100/empeg.c
View file @ 8f33e3a0
......@@ -16,15 +16,14 @@
#include "generic.h"
static struct map_desc empeg_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ EMPEG_FLASHBASE, 0x00000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash */
LAST_DESC
/* virtual physical length type */
{ EMPEG_FLASHBASE, 0x00000000, 0x00200000, MT_DEVICE } /* Flash */
};
static void __init empeg_map_io(void)
{
sa1100_map_io();
iotable_init(empeg_io_desc);
iotable_init(empeg_io_desc, ARRAY_SIZE(empeg_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 3);
......
arch/arm/mach-sa1100/flexanet.c
View file @ 8f33e3a0
......@@ -152,18 +152,17 @@ __initcall(flexanet_init);
static struct map_desc flexanet_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
{ 0xf1000000, 0x18000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Ethernet controller */
{ 0xD0000000, 0x40000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Instrument boards */
{ 0xD8000000, 0x48000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* External peripherals */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00001000, MT_DEVICE }, /* Board Control Register */
{ 0xf1000000, 0x18000000, 0x01000000, MT_DEVICE }, /* Ethernet controller */
{ 0xD0000000, 0x40000000, 0x01000000, MT_DEVICE }, /* Instrument boards */
{ 0xD8000000, 0x48000000, 0x01000000, MT_DEVICE } /* External peripherals */
};
static void __init flexanet_map_io(void)
{
sa1100_map_io();
iotable_init(flexanet_io_desc);
iotable_init(flexanet_io_desc, ARRAY_SIZE(flexanet_io_desc));
flexanet_serial_init();
/* wakeup source is GPIO-0 only */
......
arch/arm/mach-sa1100/freebird.c
View file @ 8f33e3a0
......@@ -43,8 +43,6 @@ static int __init freebird_init(void)
if (machine_is_freebird()) {
sa1100fb_backlight_power = freebird_backlight_power;
sa1100fb_lcd_power = freebird_lcd_power;
set_GPIO_IRQ_edge(GPIO_FREEBIRD_UCB1300, GPIO_RISING_EDGE);
}
return 0;
}
......@@ -52,16 +50,15 @@ static int __init freebird_init(void)
__initcall(freebird_init);
static struct map_desc freebird_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x12000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Board Control Register */
{ 0xf2000000, 0x19000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0},
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x12000000, 0x00100000, MT_DEVICE }, /* Board Control Register */
{ 0xf2000000, 0x19000000, 0x00100000, MT_DEVICE }
};
static void __init freebird_map_io(void)
{
sa1100_map_io();
iotable_init(freebird_io_desc);
iotable_init(freebird_io_desc, ARRAY_SIZE(freebird_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/generic.c
View file @ 8f33e3a0
......@@ -134,8 +134,6 @@ EXPORT_SYMBOL(sa1100fb_lcd_power);
*
* Typically, static virtual address mappings are as follow:
*
* 0xe8000000-0xefffffff: flash memory (especially when multiple flash
* banks need to be mapped contigously)
* 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
* 0xf4000000-0xf4ffffff: SA-1111
* 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
......@@ -150,17 +148,16 @@ EXPORT_SYMBOL(sa1100fb_lcd_power);
*/
static struct map_desc standard_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf8000000, 0x80000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCM */
{ 0xfa000000, 0x90000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SCM */
{ 0xfc000000, 0xa0000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* MER */
{ 0xfe000000, 0xb0000000, 0x00200000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD + DMA */
LAST_DESC
/* virtual physical length type */
{ 0xf8000000, 0x80000000, 0x00100000, MT_DEVICE }, /* PCM */
{ 0xfa000000, 0x90000000, 0x00100000, MT_DEVICE }, /* SCM */
{ 0xfc000000, 0xa0000000, 0x00100000, MT_DEVICE }, /* MER */
{ 0xfe000000, 0xb0000000, 0x00200000, MT_DEVICE } /* LCD + DMA */
};
void __init sa1100_map_io(void)
{
iotable_init(standard_io_desc);
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
}
/*
......@@ -203,3 +200,4 @@ void __init sa1110_mb_enable(void)
local_irq_restore(flags);
}
arch/arm/mach-sa1100/graphicsclient.c
View file @ 8f33e3a0
......@@ -9,7 +9,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
......@@ -121,10 +121,9 @@ static void __init graphicsclient_init_irq(void)
static struct map_desc graphicsclient_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
{ 0xf1000000, 0x18000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CAN */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00400000, MT_DEVICE }, /* CPLD */
{ 0xf1000000, 0x18000000, 0x00400000, MT_DEVICE } /* CAN */
};
static u_int graphicsclient_get_mctrl(struct uart_port *port)
......@@ -187,7 +186,7 @@ static struct sa1100_port_fns graphicsclient_port_fns __initdata = {
static void __init graphicsclient_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsclient_io_desc);
iotable_init(graphicsclient_io_desc, ARRAY_SIZE(graphicsclient_io_desc));
sa1100_register_uart_fns(&graphicsclient_port_fns);
sa1100_register_uart(0, 3);
......
arch/arm/mach-sa1100/graphicsmaster.c
View file @ 8f33e3a0
......@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
......@@ -153,11 +153,10 @@ static void __init graphicsmaster_init_irq(void)
static struct map_desc graphicsmaster_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */
{ 0xf1000000, 0x40000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CAN */
{ 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00400000, MT_DEVICE }, /* CPLD */
{ 0xf1000000, 0x40000000, 0x00400000, MT_DEVICE }, /* CAN */
{ 0xf4000000, 0x18000000, 0x00800000, MT_DEVICE } /* SA-1111 */
};
#error Old code. Someone needs to decide what to do about this.
......@@ -244,7 +243,7 @@ static struct sa1100_port_fns graphicsmaster_port_fns __initdata = {
static void __init graphicsmaster_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsmaster_io_desc);
iotable_init(graphicsmaster_io_desc, ARRAY_SIZE(graphicsmaster_io_desc));
sa1100_register_uart_fns(&graphicsmaster_port_fns);
sa1100_register_uart(0, 3);
......
arch/arm/mach-sa1100/h3600.c
View file @ 8f33e3a0
......@@ -434,17 +434,16 @@ static struct sa1100_port_fns h3600_port_fns __initdata = {
};
static struct map_desc h3600_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ H3600_EGPIO_VIRT, 0x49000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 CS#5 */
{ H3600_BANK_2_VIRT, 0x10000000, 0x02800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 2 CS#2 */
{ H3600_BANK_4_VIRT, 0x40000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 4 CS#4 */
LAST_DESC
/* virtual physical length type */
{ H3600_EGPIO_VIRT, 0x49000000, 0x01000000, MT_DEVICE }, /* EGPIO 0 CS#5 */
{ H3600_BANK_2_VIRT, 0x10000000, 0x02800000, MT_DEVICE }, /* static memory bank 2 CS#2 */
{ H3600_BANK_4_VIRT, 0x40000000, 0x00800000, MT_DEVICE } /* static memory bank 4 CS#4 */
};
static void __init h3600_map_io(void)
{
sa1100_map_io();
iotable_init(h3600_io_desc);
iotable_init(h3600_io_desc, ARRAY_SIZE(h3600_io_desc));
sa1100_register_uart_fns(&h3600_port_fns);
sa1100_register_uart(0, 3);
......
arch/arm/mach-sa1100/huw_webpanel.c
View file @ 8f33e3a0
......@@ -60,16 +60,15 @@ __initcall(init_huw_cs3);
area size = 288 kByte (0x48000 Bytes)
**/
static struct map_desc huw_webpanel_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0xc1fb8000, 0x00048000, DOMAIN_IO, 0, 1, 0, 0 }, /* Parameter */
{ 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0xc1fb8000, 0x00048000, MT_DEVICE }, /* Parameter */
{ 0xf1000000, 0x18000000, 0x00100000, MT_DEVICE } /* Paules CS3, write only */
};
static void __init huw_webpanel_map_io(void)
{
sa1100_map_io();
iotable_init(huw_webpanel_io_desc);
iotable_init(huw_webpanel_io_desc, ARRAY_SIZE(huw_webpanel_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/itsy.c
View file @ 8f33e3a0
......@@ -18,16 +18,14 @@
/* BRADFIXME The egpio addresses aren't verifiably correct. (i.e. they're most
likely wrong. */
static struct map_desc itsy_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
{ 0xf0000000, 0x49000000, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x49000000, 0x01000000, MT_DEVICE } /* EGPIO 0 */
};
static void __init itsy_map_io(void)
{
sa1100_map_io();
iotable_init(itsy_io_desc);
iotable_init(itsy_io_desc, ARRAY_SIZE(itsy_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/jornada720.c
View file @ 8f33e3a0
......@@ -56,17 +56,16 @@ static int __init jornada720_init(void)
__initcall(jornada720_init);
static struct map_desc jornada720_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x48000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Epson registers */
{ 0xf1000000, 0x48200000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Epson frame buffer */
{ 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Epson registers */
{ 0xf1000000, 0x48200000, 0x00100000, MT_DEVICE }, /* Epson frame buffer */
{ 0xf4000000, 0x40000000, 0x00100000, MT_DEVICE } /* SA-1111 */
};
static void __init jornada720_map_io(void)
{
sa1100_map_io();
iotable_init(jornada720_io_desc);
iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/lart.c
View file @ 8f33e3a0
......@@ -17,16 +17,15 @@
static struct map_desc lart_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash memory */
{ 0xec000000, 0x08000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash, alternative location */
LAST_DESC
/* virtual physical length type */
{ 0xe8000000, 0x00000000, 0x00400000, MT_DEVICE }, /* main flash memory */
{ 0xec000000, 0x08000000, 0x00400000, MT_DEVICE } /* main flash, alternative location */
};
static void __init lart_map_io(void)
{
sa1100_map_io();
iotable_init(lart_io_desc);
iotable_init(lart_io_desc, ARRAY_SIZE(lart_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/nanoengine.c
View file @ 8f33e3a0
......@@ -25,17 +25,15 @@ fixup_nanoengine(struct machine_desc *desc, struct tag *tags,
}
static struct map_desc nanoengine_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
{ 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
{ 0xf1000000, 0x18A00000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Internal PCI Config Space */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00100000, MT_DEVICE }, /* System Registers */
{ 0xf1000000, 0x18A00000, 0x00100000, MT_DEVICE } /* Internal PCI Config Space */
};
static void __init nanoengine_map_io(void)
{
sa1100_map_io();
iotable_init(nanoengine_io_desc);
iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 2);
......
arch/arm/mach-sa1100/neponset.c
View file @ 8f33e3a0
......@@ -2,7 +2,7 @@
* linux/arch/arm/mach-sa1100/neponset.c
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
......@@ -18,7 +18,9 @@
#include <asm/mach/irq.h>
#include <asm/mach/serial_sa1100.h>
#include <asm/arch/assabet.h>
#include <asm/arch/neponset.h>
#include <asm/hardware/sa1111.h>
#include <asm/sizes.h>
#include "sa1111.h"
......@@ -216,13 +218,12 @@ static int __init neponset_init(void)
__initcall(neponset_init);
static struct map_desc neponset_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf3000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
{ 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf3000000, 0x10000000, SZ_1M, MT_DEVICE }, /* System Registers */
{ 0xf4000000, 0x40000000, SZ_1M, MT_DEVICE } /* SA-1111 */
};
void __init neponset_map_io(void)
{
iotable_init(neponset_io_desc);
iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc));
}
arch/arm/mach-sa1100/omnimeter.c
View file @ 8f33e3a0
......@@ -41,15 +41,14 @@ static int __init omnimeter_init(void)
__initcall(omnimeter_init);
static struct map_desc omnimeter_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xd2000000, 0x10000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* TS */
LAST_DESC
/* virtual physical length type */
{ 0xd2000000, 0x10000000, 0x02000000, MT_DEVICE } /* TS */
};
static void __init omnimeter_map_io(void)
{
sa1100_map_io();
iotable_init(omnimeter_io_desc);
iotable_init(omnimeter_io_desc, ARRAY_SIZE(omnimeter_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/pangolin.c
View file @ 8f33e3a0
......@@ -16,15 +16,14 @@
#include "generic.h"
static struct map_desc pangolin_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
LAST_DESC
/* virtual physical length type */
{ 0xf2800000, 0x4b800000, 0x00800000, MT_DEVICE } /* MQ200 */
};
static void __init pangolin_map_io(void)
{
sa1100_map_io();
iotable_init(pangolin_io_desc);
iotable_init(pangolin_io_desc, ARRAY_SIZE(pangolin_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 3);
......
arch/arm/mach-sa1100/pfs168.c
View file @ 8f33e3a0
......@@ -56,28 +56,26 @@ static void __init pfs168_init_irq(void)
}
static struct map_desc pfs168_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
{ 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* 16C752 DUART port A (COM5) */
{ 0xf0001000, 0x10800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* 16C752 DUART port B (COM6) */
{ 0xf0002000, 0x11000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM1 RTS control (SYSC1RTS) */
{ 0xf0003000, 0x11400000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Status LED control (SYSLED) */
{ 0xf0004000, 0x11800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* DTMF code read (SYSDTMF) */
{ 0xf0005000, 0x11c00000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD configure, enable (SYSLCDDE) */
{ 0xf0006000, 0x12000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM1 DSR and motion sense (SYSC1DSR) */
{ 0xf0007000, 0x12800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* COM3 xmit enable (SYSC3TEN) */
{ 0xf0008000, 0x13000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Control register A (SYSCTLA) */
{ 0xf0009000, 0x13800000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* Control register B (SYSCTLB) */
{ 0xf000a000, 0x18000000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, /* SMC91C96 */
{ 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
{ 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00001000, MT_DEVICE }, /* 16C752 DUART port A (COM5) */
{ 0xf0001000, 0x10800000, 0x00001000, MT_DEVICE }, /* 16C752 DUART port B (COM6) */
{ 0xf0002000, 0x11000000, 0x00001000, MT_DEVICE }, /* COM1 RTS control (SYSC1RTS) */
{ 0xf0003000, 0x11400000, 0x00001000, MT_DEVICE }, /* Status LED control (SYSLED) */
{ 0xf0004000, 0x11800000, 0x00001000, MT_DEVICE }, /* DTMF code read (SYSDTMF) */
{ 0xf0005000, 0x11c00000, 0x00001000, MT_DEVICE }, /* LCD configure, enable (SYSLCDDE) */
{ 0xf0006000, 0x12000000, 0x00001000, MT_DEVICE }, /* COM1 DSR and motion sense (SYSC1DSR) */
{ 0xf0007000, 0x12800000, 0x00001000, MT_DEVICE }, /* COM3 xmit enable (SYSC3TEN) */
{ 0xf0008000, 0x13000000, 0x00001000, MT_DEVICE }, /* Control register A (SYSCTLA) */
{ 0xf0009000, 0x13800000, 0x00001000, MT_DEVICE }, /* Control register B (SYSCTLB) */
{ 0xf000a000, 0x18000000, 0x00001000, MT_DEVICE }, /* SMC91C96 */
{ 0xf2800000, 0x4b800000, 0x00800000, MT_DEVICE }, /* MQ200 */
{ 0xf4000000, 0x40000000, 0x00100000, MT_DEVICE } /* SA-1111 */
};
static void __init pfs168_map_io(void)
{
sa1100_map_io();
iotable_init(pfs168_io_desc);
iotable_init(pfs168_io_desc, ARRAY_SIZE(pfs168_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/pleb.c
View file @ 8f33e3a0
......@@ -15,17 +15,9 @@
#include "generic.h"
static struct map_desc pleb_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash memory */
{ 0xe8400000, 0x08000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* main flash, alternative location */
LAST_DESC
};
static void __init pleb_map_io(void)
{
sa1100_map_io();
iotable_init(pleb_io_desc);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/pm.c
View file @ 8f33e3a0
......@@ -18,12 +18,14 @@
* 2001-08-29: Nicolas Pitre <nico@cam.org>
* Cleaned up, pushed platform dependent stuff
* in the platform specific files.
*
* 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
* Storage is local on the stack now.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/sysctl.h>
......@@ -35,7 +37,6 @@
#include <asm/system.h>
#include <asm/leds.h>
#include "sleep.h"
/*
* Debug macros
......@@ -45,20 +46,32 @@
extern void sa1100_cpu_suspend(void);
extern void sa1100_cpu_resume(void);
extern unsigned long *sleep_save; /* virtual address */
extern unsigned long sleep_save_p; /* physical address */
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
/*
* List of global SA11x0 peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
* on the stack and then the stack pointer is stored last in sleep.S.
*/
enum { SLEEP_SAVE_SP = 0,
SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
SLEEP_SAVE_GPDR, SLEEP_SAVE_GRER, SLEEP_SAVE_GFER, SLEEP_SAVE_GAFR,
SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
SLEEP_SAVE_ICMR,
SLEEP_SAVE_Ser1SDCR0,
SLEEP_SAVE_SIZE
};
int pm_do_suspend(void)
{
/* set up pointer to sleep parameters */
sleep_save = kmalloc(SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC);
if (!sleep_save)
return -ENOMEM;
sleep_save_p = virt_to_phys(sleep_save);
unsigned long sleep_save[SLEEP_SAVE_SIZE];
cli();
......@@ -146,8 +159,6 @@ int pm_do_suspend(void)
sti();
kfree (sleep_save);
/*
* Restore the CPU frequency settings.
*/
......@@ -158,6 +169,11 @@ int pm_do_suspend(void)
return 0;
}
unsigned long sleep_phys_sp(void *sp)
{
return virt_to_phys(sp);
}
#ifdef CONFIG_SYSCTL
/*
* ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than
......
arch/arm/mach-sa1100/simpad.c
View file @ 8f33e3a0
/*
* linux/arch/arm/mach-sa1100/simpad.c
*
*/
#include <linux/config.h>
......@@ -41,10 +40,9 @@ void clear_cs3_bit(int value)
}
static struct map_desc simpad_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* MQ200 */
{ 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */
LAST_DESC
/* virtual physical length type */
{ 0xf2800000, 0x4b800000, 0x00800000, MT_DEVICE }, /* MQ200 */
{ 0xf1000000, 0x18000000, 0x00100000, MT_DEVICE } /* Paules CS3, write only */
};
......@@ -65,7 +63,7 @@ static struct sa1100_port_fns simpad_port_fns __initdata = {
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc);
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
PSPR = 0xc0008000;
GPDR &= ~GPIO_GPIO0;
......
arch/arm/mach-sa1100/sleep.S
View file @ 8f33e3a0
......@@ -11,12 +11,20 @@
* 2001-02-06: Cliff Brake Initial code
*
* 2001-08-29: Nicolas Pitre Simplified.
*
* 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
* Storage is on the stack now.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
#include "sleep.h"
.text
/*
* sa1100_cpu_suspend()
......@@ -25,35 +33,24 @@
*
*/
.text
ENTRY(sa1100_cpu_suspend)
ENTRY(sleep_save) .word 0 @ virtual address of parameter array
ENTRY(sleep_save_p) .word 0 @ physical address of parameter array
stmfd sp!, {r4 - r12, lr} @ save registers on stack
ENTRY(sa1100_cpu_suspend)
@ get coprocessor registers
mrc p15, 0, r4, c3, c0, 0 @ domain ID
mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
mrc p15, 0, r6, c13, c0, 0 @ PID
mrc p15, 0, r7, c1, c0, 0 @ control reg
@ store them plus current virtual stack ptr on stack
stmfd sp!, {r4 - r7, sp}
@ save registers on stack
stmfd sp!, {r4 - r12, lr}
@ load virtual address for sleep_save array
ldr r4, sleep_save
@ save stack pointer
str sp, [r4, #(SLEEP_SAVE_SP*4)]
@ save coprocessor registers
mrc p15, 0, r1, c1, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R1*4)]
mrc p15, 0, r1, c2, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R2*4)]
mrc p15, 0, r1, c3, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R3*4)]
mrc p15, 0, r1, c5, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R5*4)]
mrc p15, 0, r1, c6, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R6*4)]
mrc p15, 0, r1, c13, c0, 0
str r1, [r4, #(SLEEP_SAVE_CP15_R13*4)]
@ preserve phys address of stack
mov r0, sp
bl sleep_phys_sp
ldr r1, =sleep_save_sp
str r0, [r1]
@ clean data cache and invalidate WB
bl cpu_sa1100_cache_clean_invalidate_all
......@@ -79,25 +76,24 @@ ENTRY(sa1100_cpu_suspend)
mov r0, #90
bl udelay
/* setup up register contents for jump to page containing SA1110 SDRAM controller bug fix suspend code
*
* r0 points to MSC0 register
* r1 points to MSC1 register
* r2 points to MSC2 register
* r3 is MSC0 value
* r4 is MSC1 value
* r5 is MSC2 value
* r6 points to MDREFR register
* r7 is first MDREFR value
* r8 is second MDREFR value
* r9 is pointer to MDCNFG register
* r10 is MDCNFG value
* r11 is third MDREFR value
* r12 is pointer to PMCR register
* r13 is PMCR value (1)
*
*/
/*
* SA1110 SDRAM controller workaround. register values:
*
* r0 = &MSC0
* r1 = &MSC1
* r2 = &MSC2
* r3 = MSC0 value
* r4 = MSC1 value
* r5 = MSC2 value
* r6 = &MDREFR
* r7 = first MDREFR value
* r8 = second MDREFR value
* r9 = &MDCNFG
* r10 = MDCNFG value
* r11 = third MDREFR value
* r12 = &PMCR
* r13 = PMCR value (1)
*/
ldr r0, =MSC0
ldr r1, =MSC1
......@@ -170,69 +166,49 @@ sa1110_sdram_controller_fix:
*
* entry point from bootloader into kernel during resume
*
* Note: Yes, part of the following code is located into the .data section.
* This is to allow sleep_save_sp to be accessed with a relative load
* while we can't rely on any MMU translation. We could have put
* sleep_save_sp in the .text section as well, but some setups might
* insist on it to be truely read-only.
*/
.data
.align 5
ENTRY(sa1100_cpu_resume)
@ set SVC, irqs off
mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
msr cpsr_c, r0
@ load physical address of sleep_save
ldr r4, sleep_save_p
msr cpsr_c, r0 @ set SVC, irqs off
@ restore cp15_r3, domain id
ldr r1, [r4, #(SLEEP_SAVE_CP15_R3*4)]
mcr p15, 0, r1, c3, c0 ,0
@ restore cp15_r2, translation table base address
ldr r1, [r4, #(SLEEP_SAVE_CP15_R2*4)]
mcr p15, 0, r1, c2, c0 ,0
ldr r0, sleep_save_sp @ stack phys addr
ldr r2, =resume_after_mmu @ its absolute virtual address
ldmfd r0, {r4 - r7, sp} @ CP regs + virt stack ptr
mov r1, #0
mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
@ get saved cp15 r1 (control register)
ldr r1, [r4, #(SLEEP_SAVE_CP15_R1*4)]
@ get address to jump to after turning on MMU
ldr r2, =resume_after_mmu
cmp r2, #0
b resume_turn_on_mmu
mcr p15, 0, r4, c3, c0, 0 @ domain ID
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
mcr p15, 0, r6, c13, c0, 0 @ PID
b resume_turn_on_mmu @ cache align execution
.align 5
resume_turn_on_mmu:
@ turn on mmu
mcr p15, 0, r1, c1, c0 ,0
@ jump to resume_after_mmu
mov pc, r2
mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, caches, etc.
nop
mov pc, r2 @ jump to virtual addr
nop
nop
nop
.align 5
resume_after_mmu:
@ load virtual address for sleep_save array
ldr r4, sleep_save
@ restore the rest of CPU state
ldr r1, [r4, #(SLEEP_SAVE_CP15_R13*4)]
mcr p15, 0, r1, c13, c0, 0
ldr r1, [r4, #(SLEEP_SAVE_CP15_R5*4)]
mcr p15, 0, r1, c5, c0 ,0
ldr r1, [r4, #(SLEEP_SAVE_CP15_R6*4)]
mcr p15, 0, r1, c6, c0 ,0
@ restore stack pointer
ldr sp, [r4, #(SLEEP_SAVE_SP*4)]
sleep_save_sp:
.word 0 @ preserve stack phys ptr here
@ return to caller
ldmfd sp!, {r4 - r12, pc}
.text
resume_after_mmu:
mcr p15, 0, r1, c15, c1, 2 @ enable clock switching
ldmfd sp!, {r4 - r12, pc} @ return to caller
arch/arm/mach-sa1100/sleep.h deleted 100644 → 0
View file @ afcab5c2
/*
* Offsets for register values preserved in RAM while in sleep mode
*/
#define SLEEP_SAVE_OSCR 0
#define SLEEP_SAVE_OSMR0 1
#define SLEEP_SAVE_OSMR1 2
#define SLEEP_SAVE_OSMR2 3
#define SLEEP_SAVE_OSMR3 4
#define SLEEP_SAVE_OIER 5
#define SLEEP_SAVE_GPDR 6
#define SLEEP_SAVE_GRER 7
#define SLEEP_SAVE_GFER 8
#define SLEEP_SAVE_GAFR 9
#define SLEEP_SAVE_PPDR 10
#define SLEEP_SAVE_PPSR 11
#define SLEEP_SAVE_PPAR 12
#define SLEEP_SAVE_PSDR 13
#define SLEEP_SAVE_Ser1SDCR0 14
#define SLEEP_SAVE_ICMR 15
#define SLEEP_SAVE_SP 16
#define SLEEP_SAVE_CP15_R1 17
#define SLEEP_SAVE_CP15_R2 18
#define SLEEP_SAVE_CP15_R3 19
#define SLEEP_SAVE_CP15_R5 20
#define SLEEP_SAVE_CP15_R6 21
#define SLEEP_SAVE_CP15_R13 22
#define SLEEP_SAVE_SIZE 23
arch/arm/mach-sa1100/stork.c
View file @ 8f33e3a0
......@@ -304,19 +304,17 @@ stork_kbd_unexpected_up(unsigned char code)
struct map_desc stork_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
{ STORK_VM_BASE_CS1, STORK_VM_OFF_CS1, 0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */
{ 0xf1000000, 0x10000000, 0x02800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 2 */
{ 0xf3800000, 0x40000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* static memory bank 4 */
LAST_DESC
/* virtual physical length type */
{ STORK_VM_BASE_CS1, STORK_VM_OFF_CS1, 0x01000000, MT_DEVICE }, /* EGPIO 0 */
{ 0xf1000000, 0x10000000, 0x02800000, MT_DEVICE }, /* static memory bank 2 */
{ 0xf3800000, 0x40000000, 0x00800000, MT_DEVICE } /* static memory bank 4 */
};
int __init
stork_map_io(void)
{
sa1100_map_io();
iotable_init(stork_io_desc);
iotable_init(stork_io_desc, ARRAY_SIZE(stork_io_desc));
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(1, 2);
......
arch/arm/mach-sa1100/system3.c
View file @ 8f33e3a0
......@@ -95,10 +95,9 @@ static void system3_backlight_power(int on);
*/
static struct map_desc system3_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf3000000, PT_CPLD_BASE, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
{ 0xf4000000, PT_SA1111_BASE, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf3000000, PT_CPLD_BASE, 0x00100000, MT_DEVICE }, /* System Registers */
{ 0xf4000000, PT_SA1111_BASE, 0x00100000, MT_DEVICE } /* SA-1111 */
};
static struct sa1100_port_fns system3_port_fns __initdata = {
......@@ -119,7 +118,7 @@ static void __init system3_map_io(void)
{
DPRINTK( "%s\n", "START" );
sa1100_map_io();
iotable_init(system3_io_desc);
iotable_init(system3_io_desc, ARRAY_SIZE(system3_io_desc));
sa1100_register_uart_fns(&system3_port_fns);
sa1100_register_uart(0, 1); /* com port */
......
arch/arm/mach-sa1100/xp860.c
View file @ 8f33e3a0
......@@ -57,17 +57,16 @@ static int __init xp860_init(void)
__initcall(xp860_init);
static struct map_desc xp860_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xf0000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SCSI */
{ 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* LAN */
{ 0xf4000000, 0x40000000, 0x00800000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x10000000, 0x00100000, MT_DEVICE }, /* SCSI */
{ 0xf1000000, 0x18000000, 0x00100000, MT_DEVICE }, /* LAN */
{ 0xf4000000, 0x40000000, 0x00800000, MT_DEVICE } /* SA-1111 */
};
static void __init xp860_map_io(void)
{
sa1100_map_io();
iotable_init(xp860_io_desc);
iotable_init(xp860_io_desc, ARRAY_SIZE(xp860_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
......
arch/arm/mach-sa1100/yopy.c
View file @ 8f33e3a0
......@@ -68,18 +68,15 @@ __initcall(yopy_hw_init);
static struct map_desc yopy_io_desc[] __initdata = {
/* virtual physical length domain r w c b */
{ 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash 0 */
{ 0xec000000, 0x08000000, 0x04000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash 1 */
{ 0xf0000000, 0x48000000, 0x00300000, DOMAIN_IO, 0, 1, 0, 0 }, /* LCD */
{ 0xf1000000, 0x10000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO */
LAST_DESC
/* virtual physical length type */
{ 0xf0000000, 0x48000000, 0x00300000, MT_DEVICE }, /* LCD */
{ 0xf1000000, 0x10000000, 0x00100000, MT_DEVICE } /* EGPIO */
};
static void __init yopy_map_io(void)
{
sa1100_map_io();
iotable_init(yopy_io_desc);
iotable_init(yopy_io_desc, ARRAY_SIZE(yopy_io_desc));
sa1100_register_uart(0, 3);
......
arch/arm/mach-shark/core.c
View file @ 8f33e3a0
......@@ -3,18 +3,11 @@
*
* Architecture specific stuff.
*/
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/elf.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/mach/map.h>
......@@ -23,13 +16,12 @@
extern void shark_init_irq(void);
static struct map_desc shark_io_desc[] __initdata = {
{ IO_BASE , IO_START , IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ IO_BASE , IO_START , IO_SIZE , MT_DEVICE }
};
static void __init shark_map_io(void)
{
iotable_init(shark_io_desc);
iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
}
MACHINE_START(SHARK, "Shark")
......
arch/arm/mach-tbox/core.c
View file @ 8f33e3a0
......@@ -6,6 +6,7 @@
*
* Extra MM routines for the Tbox architecture
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/init.h>
......@@ -57,13 +58,12 @@ static void tbox_init_irq(void)
static struct map_desc tbox_io_desc[] __initdata = {
/* See hardware.h for details */
{ IO_BASE, IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 },
LAST_DESC
{ IO_BASE, IO_START, 0x00100000, MT_DEVICE }
};
static void __init tbox_map_io(void)
{
iotable_init(tbox_io_desc);
iotable_init(tbox_io_desc, ARRAY_SIZE(tbox_io_desc));
}
MACHINE_START(TBOX, "unknown-TBOX")
......
arch/arm/mm/mm-armv.c
View file @ 8f33e3a0
......@@ -220,16 +220,9 @@ static inline void clear_mapping(unsigned long virt)
static void __init create_mapping(struct map_desc *md)
{
unsigned long virt, length;
int prot_sect, prot_pte;
int prot_sect, prot_pte, domain;
long off;
if (md->prot_read && md->prot_write &&
!md->cacheable && !md->bufferable) {
printk(KERN_WARNING "Security risk: creating user "
"accessible mapping for 0x%08lx at 0x%08lx\n",
md->physical, md->virtual);
}
if (md->virtual != vectors_base() && md->virtual < PAGE_OFFSET) {
printk(KERN_WARNING "MM: not creating mapping for "
"0x%08lx at 0x%08lx in user region\n",
......@@ -237,24 +230,49 @@ static void __init create_mapping(struct map_desc *md)
return;
}
prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
(md->prot_read ? L_PTE_USER : 0) |
(md->prot_write ? L_PTE_WRITE : 0) |
(md->cacheable ? L_PTE_CACHEABLE : 0) |
(md->bufferable ? L_PTE_BUFFERABLE : 0);
prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY;
prot_sect = PMD_TYPE_SECT;
switch (md->type) {
case MT_DEVICE:
prot_pte |= L_PTE_WRITE;
prot_sect |= PMD_SECT_AP_WRITE;
domain = DOMAIN_IO;
break;
case MT_CACHECLEAN:
prot_pte |= L_PTE_CACHEABLE | L_PTE_BUFFERABLE;
prot_sect |= PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE;
domain = DOMAIN_KERNEL;
break;
case MT_MINICLEAN:
prot_pte |= L_PTE_CACHEABLE;
prot_sect |= PMD_SECT_CACHEABLE;
domain = DOMAIN_KERNEL;
break;
case MT_VECTORS:
prot_pte |= L_PTE_EXEC | L_PTE_CACHEABLE | L_PTE_BUFFERABLE;
prot_sect |= PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE;
domain = DOMAIN_USER;
break;
case MT_MEMORY:
prot_pte |= L_PTE_WRITE | L_PTE_EXEC | L_PTE_CACHEABLE | L_PTE_BUFFERABLE;
prot_sect |= PMD_SECT_AP_WRITE | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE;
domain = DOMAIN_KERNEL;
break;
}
prot_sect = PMD_TYPE_SECT | PMD_DOMAIN(md->domain) |
(md->prot_read ? PMD_SECT_AP_READ : 0) |
(md->prot_write ? PMD_SECT_AP_WRITE : 0) |
(md->cacheable ? PMD_SECT_CACHEABLE : 0) |
(md->bufferable ? PMD_SECT_BUFFERABLE : 0);
prot_sect |= PMD_DOMAIN(domain);
virt = md->virtual;
off = md->physical - virt;
length = md->length;
while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
alloc_init_page(virt, virt + off, md->domain, prot_pte);
alloc_init_page(virt, virt + off, domain, prot_pte);
virt += PAGE_SIZE;
length -= PAGE_SIZE;
......@@ -268,7 +286,7 @@ static void __init create_mapping(struct map_desc *md)
}
while (length >= PAGE_SIZE) {
alloc_init_page(virt, virt + off, md->domain, prot_pte);
alloc_init_page(virt, virt + off, domain, prot_pte);
virt += PAGE_SIZE;
length -= PAGE_SIZE;
......@@ -319,12 +337,7 @@ void __init memtable_init(struct meminfo *mi)
p->physical = mi->bank[i].start;
p->virtual = __phys_to_virt(p->physical);
p->length = mi->bank[i].size;
p->domain = DOMAIN_KERNEL;
p->prot_read = 0;
p->prot_write = 1;
p->cacheable = 1;
p->bufferable = 1;
p->type = MT_MEMORY;
p ++;
}
......@@ -332,12 +345,7 @@ void __init memtable_init(struct meminfo *mi)
p->physical = FLUSH_BASE_PHYS;
p->virtual = FLUSH_BASE;
p->length = PGDIR_SIZE;
p->domain = DOMAIN_KERNEL;
p->prot_read = 1;
p->prot_write = 0;
p->cacheable = 1;
p->bufferable = 1;
p->type = MT_CACHECLEAN;
p ++;
#endif
......@@ -345,12 +353,7 @@ void __init memtable_init(struct meminfo *mi)
p->physical = FLUSH_BASE_PHYS + PGDIR_SIZE;
p->virtual = FLUSH_BASE_MINICACHE;
p->length = PGDIR_SIZE;
p->domain = DOMAIN_KERNEL;
p->prot_read = 1;
p->prot_write = 0;
p->cacheable = 1;
p->bufferable = 0;
p->type = MT_MINICLEAN;
p ++;
#endif
......@@ -380,25 +383,22 @@ void __init memtable_init(struct meminfo *mi)
init_maps->physical = virt_to_phys(init_maps);
init_maps->virtual = vectors_base();
init_maps->length = PAGE_SIZE;
init_maps->domain = DOMAIN_USER;
init_maps->prot_read = 0;
init_maps->prot_write = 0;
init_maps->cacheable = 1;
init_maps->bufferable = 0;
init_maps->type = MT_VECTORS;
create_mapping(init_maps);
flush_cache_all();
flush_tlb_all();
}
/*
* Create the architecture specific mappings
*/
void __init iotable_init(struct map_desc *io_desc)
void __init iotable_init(struct map_desc *io_desc, int nr)
{
int i;
for (i = 0; io_desc[i].last == 0; i++)
for (i = 0; i < nr; i++)
create_mapping(io_desc + i);
}
......
arch/cris/drivers/sync_serial.c
View file @ 8f33e3a0
......@@ -551,7 +551,8 @@ static ssize_t sync_serial_manual_write(struct file * file, const char * buf,
}
port = &ports[dev];
copy_from_user(port->out_buffer, buf, count);
if (copy_from_user(port->out_buffer, buf, count))
return -EFAULT;
port->outp = port->out_buffer;
port->out_count = count;
port->odd_output = 1;
......@@ -597,7 +598,8 @@ static ssize_t sync_serial_write(struct file * file, const char * buf,
return sync_serial_manual_write(file, buf, count, ppos);
}
copy_from_user(port->out_buffer, buf, count);
if (copy_from_user(port->out_buffer, buf, count))
return -EFAULT;
add_wait_queue(&port->out_wait_q, &wait);
set_current_state(TASK_INTERRUPTIBLE);
start_dma(port, buf, count);
......@@ -658,7 +660,8 @@ static ssize_t sync_serial_read(struct file * file, char * buf,
avail = port->in_buffer + IN_BUFFER_SIZE - start;
count = count > avail ? avail : count;
copy_to_user(buf, start, count);
if (copy_to_user(buf, start, count))
return -EFAULT;
/* Disable interrupts while updating readp */
save_flags(flags);
......
arch/i386/Makefile
View file @ 8f33e3a0
......@@ -145,6 +145,7 @@ bzdisk: vmlinux
@$(MAKEBOOT) BOOTIMAGE=bzImage zdisk
install: vmlinux
@echo 'Cleaning up (arch)'
@$(MAKEBOOT) BOOTIMAGE=bzImage install
archclean:
......
arch/i386/boot/Makefile
View file @ 8f33e3a0
......@@ -31,11 +31,11 @@ BOOT_INCL = $(TOPDIR)/include/linux/config.h \
$(TOPDIR)/include/linux/autoconf.h \
$(TOPDIR)/include/asm/boot.h
zImage: $(CONFIGURE) bootsect setup compressed/vmlinux tools/build
zImage: bootsect setup compressed/vmlinux tools/build
$(OBJCOPY) compressed/vmlinux compressed/vmlinux.out
tools/build bootsect setup compressed/vmlinux.out $(ROOT_DEV) > zImage
bzImage: $(CONFIGURE) bbootsect bsetup compressed/bvmlinux tools/build
bzImage: bbootsect bsetup compressed/bvmlinux tools/build
$(OBJCOPY) compressed/bvmlinux compressed/bvmlinux.out
tools/build -b bbootsect bsetup compressed/bvmlinux.out $(ROOT_DEV) > bzImage
......@@ -48,14 +48,14 @@ compressed/bvmlinux: $(TOPDIR)/vmlinux
zdisk: $(BOOTIMAGE)
dd bs=8192 if=$(BOOTIMAGE) of=/dev/fd0
zlilo: $(CONFIGURE) $(BOOTIMAGE)
zlilo: $(BOOTIMAGE)
if [ -f $(INSTALL_PATH)/vmlinuz ]; then mv $(INSTALL_PATH)/vmlinuz $(INSTALL_PATH)/vmlinuz.old; fi
if [ -f $(INSTALL_PATH)/System.map ]; then mv $(INSTALL_PATH)/System.map $(INSTALL_PATH)/System.old; fi
cat $(BOOTIMAGE) > $(INSTALL_PATH)/vmlinuz
cp $(TOPDIR)/System.map $(INSTALL_PATH)/
if [ -x /sbin/lilo ]; then /sbin/lilo; else /etc/lilo/install; fi
install: $(CONFIGURE) $(BOOTIMAGE)
install: $(BOOTIMAGE)
sh -x ./install.sh $(KERNELRELEASE) $(BOOTIMAGE) $(TOPDIR)/System.map "$(INSTALL_PATH)"
tools/build: tools/build.c
......@@ -100,7 +100,8 @@ bsetup.s: setup.S video.S Makefile $(BOOT_INCL) $(TOPDIR)/include/linux/version.
dep:
clean:
rm -f tools/build
rm -f setup bootsect zImage compressed/vmlinux.out
rm -f bsetup bbootsect bzImage compressed/bvmlinux.out
@echo 'Cleaning up (boot)'
@rm -f tools/build
@rm -f setup bootsect zImage compressed/vmlinux.out
@rm -f bsetup bbootsect bzImage compressed/bvmlinux.out
@$(MAKE) -C compressed clean
arch/i386/boot/compressed/Makefile
View file @ 8f33e3a0
......@@ -47,4 +47,4 @@ piggy.o: $(SYSTEM)
rm -f $$tmppiggy $$tmppiggy.gz $$tmppiggy.lnk
clean:
rm -f vmlinux bvmlinux _tmp_*
@rm -f vmlinux bvmlinux _tmp_*
arch/i386/config.in
View file @ 8f33e3a0
......@@ -209,9 +209,26 @@ fi
endmenu
mainmenu_option next_comment
comment 'General options'
comment 'Power management options (ACPI, APM)'
source drivers/acpi/Config.in
bool 'Power Management support' CONFIG_PM
dep_tristate ' Advanced Power Management BIOS support' CONFIG_APM $CONFIG_PM
if [ "$CONFIG_APM" != "n" ]; then
bool ' Ignore USER SUSPEND' CONFIG_APM_IGNORE_USER_SUSPEND
bool ' Enable PM at boot time' CONFIG_APM_DO_ENABLE
bool ' Make CPU Idle calls when idle' CONFIG_APM_CPU_IDLE
bool ' Enable console blanking using APM' CONFIG_APM_DISPLAY_BLANK
bool ' RTC stores time in GMT' CONFIG_APM_RTC_IS_GMT
bool ' Allow interrupts during APM BIOS calls' CONFIG_APM_ALLOW_INTS
bool ' Use real mode APM BIOS call to power off' CONFIG_APM_REAL_MODE_POWER_OFF
fi
endmenu
mainmenu_option next_comment
comment 'Bus options (PCI, PCMCIA, EISA, MCA, ISA)'
# Visual Workstation support is utterly broken.
# If you want to see it working mail an VW540 to hch@infradead.org 8)
......@@ -260,6 +277,11 @@ else
define_bool CONFIG_HOTPLUG_PCI n
fi
endmenu
mainmenu_option next_comment
comment 'Executable file formats'
if [ "$CONFIG_PROC_FS" = "y" ]; then
choice 'Kernel core (/proc/kcore) format' \
"ELF CONFIG_KCORE_ELF \
......@@ -269,19 +291,6 @@ tristate 'Kernel support for a.out binaries' CONFIG_BINFMT_AOUT
tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF
tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
bool 'Power Management support' CONFIG_PM
dep_tristate ' Advanced Power Management BIOS support' CONFIG_APM $CONFIG_PM
if [ "$CONFIG_APM" != "n" ]; then
bool ' Ignore USER SUSPEND' CONFIG_APM_IGNORE_USER_SUSPEND
bool ' Enable PM at boot time' CONFIG_APM_DO_ENABLE
bool ' Make CPU Idle calls when idle' CONFIG_APM_CPU_IDLE
bool ' Enable console blanking using APM' CONFIG_APM_DISPLAY_BLANK
bool ' RTC stores time in GMT' CONFIG_APM_RTC_IS_GMT
bool ' Allow interrupts during APM BIOS calls' CONFIG_APM_ALLOW_INTS
bool ' Use real mode APM BIOS call to power off' CONFIG_APM_REAL_MODE_POWER_OFF
fi
endmenu
source drivers/mtd/Config.in
......
arch/i386/kernel/Makefile
View file @ 8f33e3a0
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
EXTRA_TARGETS := head.o init_task.o
EXTRA_TARGETS := kernel.o head.o init_task.o
O_TARGET := kernel.o
......@@ -13,8 +13,10 @@ obj-y := process.o semaphore.o signal.o entry.o traps.o irq.o vm86.o \
pci-dma.o i386_ksyms.o i387.o bluesmoke.o dmi_scan.o \
bootflag.o
obj-y += cpu/
obj-$(CONFIG_X86_BIOS_REBOOT) += reboot.o
obj-$(CONFIG_MCA) += mca.o
obj-$(CONFIG_EISA) += eisa.o
obj-$(CONFIG_MTRR) += mtrr.o
obj-$(CONFIG_X86_MSR) += msr.o
obj-$(CONFIG_X86_CPUID) += cpuid.o
......@@ -23,7 +25,9 @@ obj-$(CONFIG_APM) += apm.o
obj-$(CONFIG_X86_SMP) += smp.o smpboot.o trampoline.o
obj-$(CONFIG_X86_LOCAL_APIC) += apic.o nmi.o
obj-$(CONFIG_X86_IO_APIC) += io_apic.o
obj-$(CONFIG_SOFTWARE_SUSPEND) += suspend.o
obj-$(CONFIG_ACPI_SLEEP) += suspend.o
EXTRA_AFLAGS := -traditional
EXTRA_AFLAGS := -traditional
include $(TOPDIR)/Rules.make
arch/i386/kernel/bluesmoke.c
View file @ 8f33e3a0
......@@ -18,8 +18,24 @@
#ifdef CONFIG_X86_MCE
/* as supported by the P4/Xeon family */
struct intel_mce_extended_msrs {
u32 eax;
u32 ebx;
u32 ecx;
u32 edx;
u32 esi;
u32 edi;
u32 ebp;
u32 esp;
u32 eflags;
u32 eip;
/* u32 *reserved[]; */
};
static int mce_disabled __initdata = 0;
static int mce_num_extended_msrs = 0;
static int banks;
......@@ -75,47 +91,73 @@ static void __init intel_init_thermal(struct cpuinfo_x86 *c)
if (!cpu_has(c, X86_FEATURE_ACC))
return; /* -ENODEV */
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
/* first check if its enabled already, in which case there might
* be some SMM goo which handles it, so we can't even put a handler
* since it might be delivered via SMI already -zwanem.
*/
if (l & (1<<3)) {
printk(KERN_DEBUG "CPU#%d: Thermal monitoring already enabled\n", cpu);
} else {
wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
printk(KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
h = apic_read(APIC_LVTTHMR);
if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
printk(KERN_DEBUG "CPU#%d: Thermal monitoring handled by SMI\n", cpu);
return; /* -EBUSY */
}
/* check whether a vector already exists */
l = apic_read(APIC_LVTTHMR);
if (l & 0xff) {
printk(KERN_DEBUG "CPU#%d: Thermal LVT already handled\n", cpu);
/* check whether a vector already exists, temporarily masked? */
if (h & APIC_VECTOR_MASK) {
printk(KERN_DEBUG "CPU#%d: Thermal LVT vector (%#x) already installed\n",
cpu, (h & APIC_VECTOR_MASK));
return; /* -EBUSY */
}
wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
printk(KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
/* The temperature transition interrupt handler setup */
l = THERMAL_APIC_VECTOR; /* our delivery vector */
l |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
apic_write_around(APIC_LVTTHMR, l);
h = THERMAL_APIC_VECTOR; /* our delivery vector */
h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
apic_write_around(APIC_LVTTHMR, h);
rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x3 , h);
wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
/* ok we're good to go... */
vendor_thermal_interrupt = intel_thermal_interrupt;
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
l = apic_read(APIC_LVTTHMR);
apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
printk(KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
return;
}
#endif /* CONFIG_X86_MCE_P4THERMAL */
/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
static int inline intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
{
u32 h;
if (mce_num_extended_msrs == 0)
goto done;
rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
/* can we rely on kmalloc to do a dynamic
* allocation for the reserved registers?
*/
done:
return mce_num_extended_msrs;
}
/*
* Machine Check Handler For PII/PIII
*/
......@@ -126,6 +168,7 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
u32 alow, ahigh, high, low;
u32 mcgstl, mcgsth;
int i;
struct intel_mce_extended_msrs dbg;
rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
if(mcgstl&(1<<0)) /* Recoverable ? */
......@@ -133,6 +176,15 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
if (intel_get_extended_msrs(&dbg)) {
printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
smp_processor_id(), dbg.eip, dbg.eflags);
printk(KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
printk(KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
}
for (i=0;i<banks;i++) {
rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
if(high&(1<<31)) {
......@@ -334,11 +386,24 @@ static void __init intel_mcheck_init(struct cpuinfo_x86 *c)
set_in_cr4(X86_CR4_MCE);
printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
/*
* Check for P4/Xeon specific MCE extensions
*/
if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 15) {
/* Check for P4/Xeon extended MCE MSRs */
rdmsr(MSR_IA32_MCG_CAP, l, h);
if (l & (1<<9)) {/* MCG_EXT_P */
mce_num_extended_msrs = (l >> 16) & 0xff;
printk(KERN_INFO "CPU#%d: Intel P4/Xeon Extended MCE MSRs (%d) available\n",
smp_processor_id(), mce_num_extended_msrs);
}
#ifdef CONFIG_X86_MCE_P4THERMAL
/* Only enable thermal throttling warning on Pentium 4. */
if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 15)
/* Check for P4/Xeon Thermal monitor */
intel_init_thermal(c);
#endif
}
done=1;
}
......
arch/i386/kernel/cpu/Makefile 0 → 100644
View file @ 8f33e3a0
#
# Makefile for x86-compatible CPU details and quirks
#
obj-y := common.o proc.o
obj-y += amd.o
obj-y += cyrix.o
obj-y += centaur.o
obj-y += transmeta.o
obj-y += intel.o
obj-y += rise.o
obj-y += nexgen.o
obj-y += umc.o
include $(TOPDIR)/Rules.make
arch/i386/kernel/cpu/amd.c 0 → 100644
View file @ 8f33e3a0
#include <linux/init.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
#include "cpu.h"
/*
* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
* misexecution of code under Linux. Owners of such processors should
* contact AMD for precise details and a CPU swap.
*
* See http://www.multimania.com/poulot/k6bug.html
* http://www.amd.com/K6/k6docs/revgd.html
*
* The following test is erm.. interesting. AMD neglected to up
* the chip setting when fixing the bug but they also tweaked some
* performance at the same time..
*/
extern void vide(void);
__asm__(".align 4\nvide: ret");
static void __init init_amd(struct cpuinfo_x86 *c)
{
u32 l, h;
int mbytes = max_mapnr >> (20-PAGE_SHIFT);
int r;
/*
* FIXME: We should handle the K5 here. Set up the write
* range and also turn on MSR 83 bits 4 and 31 (write alloc,
* no bus pipeline)
*/
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, c->x86_capability);
r = get_model_name(c);
switch(c->x86)
{
case 5:
if( c->x86_model < 6 )
{
/* Based on AMD doc 20734R - June 2000 */
if ( c->x86_model == 0 ) {
clear_bit(X86_FEATURE_APIC, c->x86_capability);
set_bit(X86_FEATURE_PGE, c->x86_capability);
}
break;
}
if ( c->x86_model == 6 && c->x86_mask == 1 ) {
const int K6_BUG_LOOP = 1000000;
int n;
void (*f_vide)(void);
unsigned long d, d2;
printk(KERN_INFO "AMD K6 stepping B detected - ");
/*
* It looks like AMD fixed the 2.6.2 bug and improved indirect
* calls at the same time.
*/
n = K6_BUG_LOOP;
f_vide = vide;
rdtscl(d);
while (n--)
f_vide();
rdtscl(d2);
d = d2-d;
/* Knock these two lines out if it debugs out ok */
printk(KERN_INFO "K6 BUG %ld %d (Report these if test report is incorrect)\n", d, 20*K6_BUG_LOOP);
printk(KERN_INFO "AMD K6 stepping B detected - ");
/* -- cut here -- */
if (d > 20*K6_BUG_LOOP)
printk("system stability may be impaired when more than 32 MB are used.\n");
else
printk("probably OK (after B9730xxxx).\n");
printk(KERN_INFO "Please see http://www.mygale.com/~poulot/k6bug.html\n");
}
/* K6 with old style WHCR */
if (c->x86_model < 8 ||
(c->x86_model== 8 && c->x86_mask < 8)) {
/* We can only write allocate on the low 508Mb */
if(mbytes>508)
mbytes=508;
rdmsr(MSR_K6_WHCR, l, h);
if ((l&0x0000FFFF)==0) {
unsigned long flags;
l=(1<<0)|((mbytes/4)<<1);
local_irq_save(flags);
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
local_irq_restore(flags);
printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
mbytes);
}
break;
}
if ((c->x86_model == 8 && c->x86_mask >7) ||
c->x86_model == 9 || c->x86_model == 13) {
/* The more serious chips .. */
if(mbytes>4092)
mbytes=4092;
rdmsr(MSR_K6_WHCR, l, h);
if ((l&0xFFFF0000)==0) {
unsigned long flags;
l=((mbytes>>2)<<22)|(1<<16);
local_irq_save(flags);
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
local_irq_restore(flags);
printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
mbytes);
}
/* Set MTRR capability flag if appropriate */
if (c->x86_model == 13 || c->x86_model == 9 ||
(c->x86_model == 8 && c->x86_mask >= 8))
set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
break;
}
break;
case 6: /* An Athlon/Duron */
/* Bit 15 of Athlon specific MSR 15, needs to be 0
* to enable SSE on Palomino/Morgan CPU's.
* If the BIOS didn't enable it already, enable it
* here.
*/
if (c->x86_model == 6 || c->x86_model == 7) {
if (!test_bit(X86_FEATURE_XMM, c->x86_capability)) {
printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
rdmsr(MSR_K7_HWCR, l, h);
l &= ~0x00008000;
wrmsr(MSR_K7_HWCR, l, h);
set_bit(X86_FEATURE_XMM, c->x86_capability);
}
}
break;
}
display_cacheinfo(c);
// return r;
}
static void amd_identify(struct cpuinfo_x86 * c)
{
u32 xlvl;
if (have_cpuid_p()) {
generic_identify(c);
/* AMD-defined flags: level 0x80000001 */
xlvl = cpuid_eax(0x80000000);
if ( (xlvl & 0xffff0000) == 0x80000000 ) {
if ( xlvl >= 0x80000001 )
c->x86_capability[1] = cpuid_edx(0x80000001);
if ( xlvl >= 0x80000004 )
get_model_name(c); /* Default name */
}
}
}
static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
/* AMD errata T13 (order #21922) */
if ((c->x86 == 6)) {
if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
size = 64;
if (c->x86_model == 4 &&
(c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
size = 256;
}
return size;
}
static struct cpu_dev amd_cpu_dev __initdata = {
c_vendor: "AMD",
c_ident: { "AuthenticAMD" },
c_models: {
{ X86_VENDOR_AMD, 4,
{
[3] "486 DX/2",
[7] "486 DX/2-WB",
[8] "486 DX/4",
[9] "486 DX/4-WB",
[14] "Am5x86-WT",
[15] "Am5x86-WB"
}
},
},
c_init: init_amd,
c_identify: amd_identify,
c_size_cache: amd_size_cache,
};
int __init amd_init_cpu(void)
{
cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
return 0;
}
//early_arch_initcall(amd_init_cpu);
arch/i386/kernel/cpu/centaur.c 0 → 100644
View file @ 8f33e3a0
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include "cpu.h"
#ifdef CONFIG_X86_OOSTORE
static u32 __init power2(u32 x)
{
u32 s=1;
while(s<=x)
s<<=1;
return s>>=1;
}
/*
* Set up an actual MCR
*/
static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)
{
u32 lo, hi;
hi = base & ~0xFFF;
lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
lo &= ~0xFFF; /* Remove the ctrl value bits */
lo |= key; /* Attribute we wish to set */
wrmsr(reg+MSR_IDT_MCR0, lo, hi);
mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
}
/*
* Figure what we can cover with MCR's
*
* Shortcut: We know you can't put 4Gig of RAM on a winchip
*/
static u32 __init ramtop(void) /* 16388 */
{
int i;
u32 top = 0;
u32 clip = 0xFFFFFFFFUL;
for (i = 0; i < e820.nr_map; i++) {
unsigned long start, end;
if (e820.map[i].addr > 0xFFFFFFFFUL)
continue;
/*
* Don't MCR over reserved space. Ignore the ISA hole
* we frob around that catastrophy already
*/
if (e820.map[i].type == E820_RESERVED)
{
if(e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
clip = e820.map[i].addr;
continue;
}
start = e820.map[i].addr;
end = e820.map[i].addr + e820.map[i].size;
if (start >= end)
continue;
if (end > top)
top = end;
}
/* Everything below 'top' should be RAM except for the ISA hole.
Because of the limited MCR's we want to map NV/ACPI into our
MCR range for gunk in RAM
Clip might cause us to MCR insufficient RAM but that is an
acceptable failure mode and should only bite obscure boxes with
a VESA hole at 15Mb
The second case Clip sometimes kicks in is when the EBDA is marked
as reserved. Again we fail safe with reasonable results
*/
if(top>clip)
top=clip;
return top;
}
/*
* Compute a set of MCR's to give maximum coverage
*/
static int __init centaur_mcr_compute(int nr, int key)
{
u32 mem = ramtop();
u32 root = power2(mem);
u32 base = root;
u32 top = root;
u32 floor = 0;
int ct = 0;
while(ct<nr)
{
u32 fspace = 0;
/*
* Find the largest block we will fill going upwards
*/
u32 high = power2(mem-top);
/*
* Find the largest block we will fill going downwards
*/
u32 low = base/2;
/*
* Don't fill below 1Mb going downwards as there
* is an ISA hole in the way.
*/
if(base <= 1024*1024)
low = 0;
/*
* See how much space we could cover by filling below
* the ISA hole
*/
if(floor == 0)
fspace = 512*1024;
else if(floor ==512*1024)
fspace = 128*1024;
/* And forget ROM space */
/*
* Now install the largest coverage we get
*/
if(fspace > high && fspace > low)
{
centaur_mcr_insert(ct, floor, fspace, key);
floor += fspace;
}
else if(high > low)
{
centaur_mcr_insert(ct, top, high, key);
top += high;
}
else if(low > 0)
{
base -= low;
centaur_mcr_insert(ct, base, low, key);
}
else break;
ct++;
}
/*
* We loaded ct values. We now need to set the mask. The caller
* must do this bit.
*/
return ct;
}
static void __init centaur_create_optimal_mcr(void)
{
int i;
/*
* Allocate up to 6 mcrs to mark as much of ram as possible
* as write combining and weak write ordered.
*
* To experiment with: Linux never uses stack operations for
* mmio spaces so we could globally enable stack operation wc
*
* Load the registers with type 31 - full write combining, all
* writes weakly ordered.
*/
int used = centaur_mcr_compute(6, 31);
/*
* Wipe unused MCRs
*/
for(i=used;i<8;i++)
wrmsr(MSR_IDT_MCR0+i, 0, 0);
}
static void __init winchip2_create_optimal_mcr(void)
{
u32 lo, hi;
int i;
/*
* Allocate up to 6 mcrs to mark as much of ram as possible
* as write combining, weak store ordered.
*
* Load the registers with type 25
* 8 - weak write ordering
* 16 - weak read ordering
* 1 - write combining
*/
int used = centaur_mcr_compute(6, 25);
/*
* Mark the registers we are using.
*/
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
for(i=0;i<used;i++)
lo|=1<<(9+i);
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
/*
* Wipe unused MCRs
*/
for(i=used;i<8;i++)
wrmsr(MSR_IDT_MCR0+i, 0, 0);
}
/*
* Handle the MCR key on the Winchip 2.
*/
static void __init winchip2_unprotect_mcr(void)
{
u32 lo, hi;
u32 key;
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
lo&=~0x1C0; /* blank bits 8-6 */
key = (lo>>17) & 7;
lo |= key<<6; /* replace with unlock key */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
}
static void __init winchip2_protect_mcr(void)
{
u32 lo, hi;
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
lo&=~0x1C0; /* blank bits 8-6 */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
}
#endif
static void __init init_centaur(struct cpuinfo_x86 *c)
{
enum {
ECX8=1<<1,
EIERRINT=1<<2,
DPM=1<<3,
DMCE=1<<4,
DSTPCLK=1<<5,
ELINEAR=1<<6,
DSMC=1<<7,
DTLOCK=1<<8,
EDCTLB=1<<8,
EMMX=1<<9,
DPDC=1<<11,
EBRPRED=1<<12,
DIC=1<<13,
DDC=1<<14,
DNA=1<<15,
ERETSTK=1<<16,
E2MMX=1<<19,
EAMD3D=1<<20,
};
char *name;
u32 fcr_set=0;
u32 fcr_clr=0;
u32 lo,hi,newlo;
u32 aa,bb,cc,dd;
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, c->x86_capability);
switch (c->x86) {
case 5:
switch(c->x86_model) {
case 4:
name="C6";
fcr_set=ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
fcr_clr=DPDC;
printk(KERN_NOTICE "Disabling bugged TSC.\n");
clear_bit(X86_FEATURE_TSC, c->x86_capability);
#ifdef CONFIG_X86_OOSTORE
centaur_create_optimal_mcr();
/* Enable
write combining on non-stack, non-string
write combining on string, all types
weak write ordering
The C6 original lacks weak read order
Note 0x120 is write only on Winchip 1 */
wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
#endif
break;
case 8:
switch(c->x86_mask) {
default:
name="2";
break;
case 7 ... 9:
name="2A";
break;
case 10 ... 15:
name="2B";
break;
}
fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
fcr_clr=DPDC;
#ifdef CONFIG_X86_OOSTORE
winchip2_unprotect_mcr();
winchip2_create_optimal_mcr();
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
/* Enable
write combining on non-stack, non-string
write combining on string, all types
weak write ordering
*/
lo|=31;
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
winchip2_protect_mcr();
#endif
break;
case 9:
name="3";
fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
fcr_clr=DPDC;
#ifdef CONFIG_X86_OOSTORE
winchip2_unprotect_mcr();
winchip2_create_optimal_mcr();
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
/* Enable
write combining on non-stack, non-string
write combining on string, all types
weak write ordering
*/
lo|=31;
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
winchip2_protect_mcr();
#endif
break;
case 10:
name="4";
/* no info on the WC4 yet */
break;
default:
name="??";
}
rdmsr(MSR_IDT_FCR1, lo, hi);
newlo=(lo|fcr_set) & (~fcr_clr);
if (newlo!=lo) {
printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo );
wrmsr(MSR_IDT_FCR1, newlo, hi );
} else {
printk(KERN_INFO "Centaur FCR is 0x%X\n",lo);
}
/* Emulate MTRRs using Centaur's MCR. */
set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
/* Report CX8 */
set_bit(X86_FEATURE_CX8, c->x86_capability);
/* Set 3DNow! on Winchip 2 and above. */
if (c->x86_model >=8)
set_bit(X86_FEATURE_3DNOW, c->x86_capability);
/* See if we can find out some more. */
if ( cpuid_eax(0x80000000) >= 0x80000005 ) {
/* Yes, we can. */
cpuid(0x80000005,&aa,&bb,&cc,&dd);
/* Add L1 data and code cache sizes. */
c->x86_cache_size = (cc>>24)+(dd>>24);
}
sprintf( c->x86_model_id, "WinChip %s", name );
break;
case 6:
switch (c->x86_model) {
case 6 ... 8: /* Cyrix III family */
rdmsr (MSR_VIA_FCR, lo, hi);
lo |= (1<<1 | 1<<7); /* Report CX8 & enable PGE */
wrmsr (MSR_VIA_FCR, lo, hi);
set_bit(X86_FEATURE_CX8, c->x86_capability);
set_bit(X86_FEATURE_3DNOW, c->x86_capability);
get_model_name(c);
display_cacheinfo(c);
break;
}
break;
}
}
static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
/* VIA C3 CPUs (670-68F) need further shifting. */
if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
size >>= 8;
return size;
}
static struct cpu_dev centaur_cpu_dev __initdata = {
c_vendor: "Centaur",
c_ident: { "CentaurHauls" },
c_init: init_centaur,
c_size_cache: centaur_size_cache,
};
int __init centaur_init_cpu(void)
{
cpu_devs[X86_VENDOR_CENTAUR] = &centaur_cpu_dev;
return 0;
}
//early_arch_initcall(centaur_init_cpu);
arch/i386/kernel/cpu/changelog 0 → 100644
View file @ 8f33e3a0
/*
* Enhanced CPU type detection by Mike Jagdis, Patrick St. Jean
* and Martin Mares, November 1997.
*
* Force Cyrix 6x86(MX) and M II processors to report MTRR capability
* and Cyrix "coma bug" recognition by
* Zoltn Bszrmnyi <zboszor@mail.externet.hu> February 1999.
*
* Force Centaur C6 processors to report MTRR capability.
* Bart Hartgers <bart@etpmod.phys.tue.nl>, May 1999.
*
* Intel Mobile Pentium II detection fix. Sean Gilley, June 1999.
*
* IDT Winchip tweaks, misc clean ups.
* Dave Jones <davej@suse.de>, August 1999
*
* Better detection of Centaur/IDT WinChip models.
* Bart Hartgers <bart@etpmod.phys.tue.nl>, August 1999.
*
* Cleaned up cache-detection code
* Dave Jones <davej@suse.de>, October 1999
*
* Added proper L2 cache detection for Coppermine
* Dragan Stancevic <visitor@valinux.com>, October 1999
*
* Added the original array for capability flags but forgot to credit
* myself :) (~1998) Fixed/cleaned up some cpu_model_info and other stuff
* Jauder Ho <jauderho@carumba.com>, January 2000
*
* Detection for Celeron coppermine, identify_cpu() overhauled,
* and a few other clean ups.
* Dave Jones <davej@suse.de>, April 2000
*
* Pentium III FXSR, SSE support
* General FPU state handling cleanups
* Gareth Hughes <gareth@valinux.com>, May 2000
*
* Added proper Cascades CPU and L2 cache detection for Cascades
* and 8-way type cache happy bunch from Intel:^)
* Dragan Stancevic <visitor@valinux.com>, May 2000
*
* Forward port AMD Duron errata T13 from 2.2.17pre
* Dave Jones <davej@suse.de>, August 2000
*
* Forward port lots of fixes/improvements from 2.2.18pre
* Cyrix III, Pentium IV support.
* Dave Jones <davej@suse.de>, October 2000
*
* Massive cleanup of CPU detection and bug handling;
* Transmeta CPU detection,
* H. Peter Anvin <hpa@zytor.com>, November 2000
*
* VIA C3 Support.
* Dave Jones <davej@suse.de>, March 2001
*
* AMD Athlon/Duron/Thunderbird bluesmoke support.
* Dave Jones <davej@suse.de>, April 2001.
*
* CacheSize bug workaround updates for AMD, Intel & VIA Cyrix.
* Dave Jones <davej@suse.de>, September, October 2001.
*
*/
arch/i386/kernel/cpu/common.c 0 → 100644
View file @ 8f33e3a0
This diff is collapsed.
arch/i386/kernel/cpu/cpu.h 0 → 100644
View file @ 8f33e3a0
struct cpu_model_info {
int vendor;
int family;
char *model_names[16];
};
/* attempt to consolidate cpu attributes */
struct cpu_dev {
char * c_vendor;
/* some have two possibilities for cpuid string */
char * c_ident[2];
struct cpu_model_info c_models[4];
void (*c_init)(struct cpuinfo_x86 * c);
void (*c_identify)(struct cpuinfo_x86 * c);
unsigned int (*c_size_cache)(struct cpuinfo_x86 * c, unsigned int size);
};
extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
extern int get_model_name(struct cpuinfo_x86 *c);
extern void display_cacheinfo(struct cpuinfo_x86 *c);
extern void generic_identify(struct cpuinfo_x86 * c);
extern int have_cpuid_p(void);
arch/i386/kernel/cpu/cyrix.c 0 → 100644
View file @ 8f33e3a0
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/processor.h>
#include "cpu.h"
/*
* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
*/
void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
unsigned char ccr2, ccr3;
unsigned long flags;
/* we test for DEVID by checking whether CCR3 is writable */
local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, ccr3 ^ 0x80);
getCx86(0xc0); /* dummy to change bus */
if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
ccr2 = getCx86(CX86_CCR2);
setCx86(CX86_CCR2, ccr2 ^ 0x04);
getCx86(0xc0); /* dummy */
if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
*dir0 = 0xfd;
else { /* Cx486S A step */
setCx86(CX86_CCR2, ccr2);
*dir0 = 0xfe;
}
}
else {
setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
/* read DIR0 and DIR1 CPU registers */
*dir0 = getCx86(CX86_DIR0);
*dir1 = getCx86(CX86_DIR1);
}
local_irq_restore(flags);
}
/*
* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
* order to identify the Cyrix CPU model after we're out of setup.c
*
* Actually since bugs.h doesnt even reference this perhaps someone should
* fix the documentation ???
*/
static unsigned char Cx86_dir0_msb __initdata = 0;
static char Cx86_model[][9] __initdata = {
"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
"M II ", "Unknown"
};
static char Cx486_name[][5] __initdata = {
"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
"SRx2", "DRx2"
};
static char Cx486S_name[][4] __initdata = {
"S", "S2", "Se", "S2e"
};
static char Cx486D_name[][4] __initdata = {
"DX", "DX2", "?", "?", "?", "DX4"
};
static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
static char cyrix_model_mult1[] __initdata = "12??43";
static char cyrix_model_mult2[] __initdata = "12233445";
/*
* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
* BIOSes for compatability with DOS games. This makes the udelay loop
* work correctly, and improves performance.
*
* FIXME: our newer udelay uses the tsc. We dont need to frob with SLOP
*/
extern void calibrate_delay(void) __init;
static void __init check_cx686_slop(struct cpuinfo_x86 *c)
{
unsigned long flags;
if (Cx86_dir0_msb == 3) {
unsigned char ccr3, ccr5;
local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
ccr5 = getCx86(CX86_CCR5);
if (ccr5 & 2)
setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
local_irq_restore(flags);
if (ccr5 & 2) { /* possible wrong calibration done */
printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
calibrate_delay();
c->loops_per_jiffy = loops_per_jiffy;
}
}
}
static void __init init_cyrix(struct cpuinfo_x86 *c)
{
unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
char *buf = c->x86_model_id;
const char *p = NULL;
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, c->x86_capability);
/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
if ( test_bit(1*32+24, c->x86_capability) ) {
clear_bit(1*32+24, c->x86_capability);
set_bit(X86_FEATURE_CXMMX, c->x86_capability);
}
do_cyrix_devid(&dir0, &dir1);
check_cx686_slop(c);
Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
/* common case step number/rev -- exceptions handled below */
c->x86_model = (dir1 >> 4) + 1;
c->x86_mask = dir1 & 0xf;
/* Now cook; the original recipe is by Channing Corn, from Cyrix.
* We do the same thing for each generation: we work out
* the model, multiplier and stepping. Black magic included,
* to make the silicon step/rev numbers match the printed ones.
*/
switch (dir0_msn) {
unsigned char tmp;
case 0: /* Cx486SLC/DLC/SRx/DRx */
p = Cx486_name[dir0_lsn & 7];
break;
case 1: /* Cx486S/DX/DX2/DX4 */
p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
: Cx486S_name[dir0_lsn & 3];
break;
case 2: /* 5x86 */
Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
p = Cx86_cb+2;
break;
case 3: /* 6x86/6x86L */
Cx86_cb[1] = ' ';
Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
if (dir1 > 0x21) { /* 686L */
Cx86_cb[0] = 'L';
p = Cx86_cb;
(c->x86_model)++;
} else /* 686 */
p = Cx86_cb+1;
/* Emulate MTRRs using Cyrix's ARRs. */
set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
/* 6x86's contain this bug */
c->coma_bug = 1;
break;
case 4: /* MediaGX/GXm */
#ifdef CONFIG_PCI
/* It isn't really a PCI quirk directly, but the cure is the
same. The MediaGX has deep magic SMM stuff that handles the
SB emulation. It thows away the fifo on disable_dma() which
is wrong and ruins the audio.
Bug2: VSA1 has a wrap bug so that using maximum sized DMA
causes bad things. According to NatSemi VSA2 has another
bug to do with 'hlt'. I've not seen any boards using VSA2
and X doesn't seem to support it either so who cares 8).
VSA1 we work around however.
*/
printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
isa_dma_bridge_buggy = 2;
#endif
c->x86_cache_size=16; /* Yep 16K integrated cache thats it */
/* GXm supports extended cpuid levels 'ala' AMD */
if (c->cpuid_level == 2) {
/* Enable Natsemi MMX extensions */
setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
get_model_name(c); /* get CPU marketing name */
/*
* The 5510/5520 companion chips have a funky PIT
* that breaks the TSC synchronizing, so turn it off
*/
if (pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, NULL) ||
pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, NULL))
clear_bit(X86_FEATURE_TSC, c->x86_capability);
return;
}
else { /* MediaGX */
Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
p = Cx86_cb+2;
c->x86_model = (dir1 & 0x20) ? 1 : 2;
#ifndef CONFIG_CS5520
clear_bit(X86_FEATURE_TSC, c->x86_capability);
#endif
}
break;
case 5: /* 6x86MX/M II */
if (dir1 > 7)
{
dir0_msn++; /* M II */
/* Enable MMX extensions (App note 108) */
setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
}
else
{
c->coma_bug = 1; /* 6x86MX, it has the bug. */
}
tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
p = Cx86_cb+tmp;
if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
(c->x86_model)++;
/* Emulate MTRRs using Cyrix's ARRs. */
set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
break;
case 0xf: /* Cyrix 486 without DEVID registers */
switch (dir0_lsn) {
case 0xd: /* either a 486SLC or DLC w/o DEVID */
dir0_msn = 0;
p = Cx486_name[(c->hard_math) ? 1 : 0];
break;
case 0xe: /* a 486S A step */
dir0_msn = 0;
p = Cx486S_name[0];
break;
}
break;
default: /* unknown (shouldn't happen, we know everyone ;-) */
dir0_msn = 7;
break;
}
strcpy(buf, Cx86_model[dir0_msn & 7]);
if (p) strcat(buf, p);
return;
}
/*
* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
* by the fact that they preserve the flags across the division of 5/2.
* PII and PPro exhibit this behavior too, but they have cpuid available.
*/
/*
* Perform the Cyrix 5/2 test. A Cyrix won't change
* the flags, while other 486 chips will.
*/
static inline int test_cyrix_52div(void)
{
unsigned int test;
__asm__ __volatile__(
"sahf\n\t" /* clear flags (%eax = 0x0005) */
"div %b2\n\t" /* divide 5 by 2 */
"lahf" /* store flags into %ah */
: "=a" (test)
: "0" (5), "q" (2)
: "cc");
/* AH is 0x02 on Cyrix after the divide.. */
return (unsigned char) (test >> 8) == 0x02;
}
static void cyrix_identify(struct cpuinfo_x86 * c)
{
/* Detect Cyrix with disabled CPUID */
if ( c->x86 == 4 && test_cyrix_52div() ) {
unsigned char dir0, dir1;
strcpy(c->x86_vendor_id, "CyrixInstead");
c->x86_vendor = X86_VENDOR_CYRIX;
/* Actually enable cpuid on the older cyrix */
/* Retrieve CPU revisions */
do_cyrix_devid(&dir0, &dir1);
dir0>>=4;
/* Check it is an affected model */
if (dir0 == 5 || dir0 == 3)
{
unsigned char ccr3, ccr4;
unsigned long flags;
printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
ccr4 = getCx86(CX86_CCR4);
setCx86(CX86_CCR4, ccr4 | 0x80); /* enable cpuid */
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
local_irq_restore(flags);
}
}
generic_identify(c);
}
static struct cpu_dev cyrix_cpu_dev __initdata = {
c_vendor: "Cyrix",
c_ident: { "CyrixInstead" },
c_init: init_cyrix,
c_identify: cyrix_identify,
};
int __init cyrix_init_cpu(void)
{
cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
return 0;
}
//early_arch_initcall(cyrix_init_cpu);
static struct cpu_dev nsc_cpu_dev __initdata = {
c_vendor: "NSC",
c_ident: { "Geode by NSC" },
c_init: init_cyrix,
c_identify: generic_identify,
};
int __init nsc_init_cpu(void)
{
cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
return 0;
}
//early_arch_initcall(nsc_init_cpu);
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#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/processor.h>
#include "cpu.h"
/* UMC chips appear to be only either 386 or 486, so no special init takes place.
*/
static void __init init_umc(struct cpuinfo_x86 * c)
{
}
static struct cpu_dev umc_cpu_dev __initdata = {
c_vendor: "UMC",
c_ident: { "UMC UMC UMC" },
c_models: {
{ X86_VENDOR_UMC, 4,
{
[1] "U5D",
[2] "U5S",
}
},
},
c_init: init_umc,
};
int __init umc_init_cpu(void)
{
cpu_devs[X86_VENDOR_UMC] = &umc_cpu_dev;
return 0;
}
//early_arch_initcall(umc_init_cpu);
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*/
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#include <asm/io.h>
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