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Commit 97539f1e authored by Ariel Elior's avatar Ariel Elior Committed by David S. Miller
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bnx2x: FW assertion changes 

This is mostly a semantic change which modifies the code parsing and printing
of FW asserts.
Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarAriel Elior <Ariel.Elior@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 58fee00f
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Showing with 85 additions and 106 deletions
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
View file @ 97539f1e
......@@ -650,119 +650,98 @@ static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
}
enum storms {
XSTORM,
TSTORM,
CSTORM,
USTORM,
MAX_STORMS
};
#define STORMS_NUM 4
#define REGS_IN_ENTRY 4
static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
enum storms storm,
int entry)
{
switch (storm) {
case XSTORM:
return XSTORM_ASSERT_LIST_OFFSET(entry);
case TSTORM:
return TSTORM_ASSERT_LIST_OFFSET(entry);
case CSTORM:
return CSTORM_ASSERT_LIST_OFFSET(entry);
case USTORM:
return USTORM_ASSERT_LIST_OFFSET(entry);
case MAX_STORMS:
default:
BNX2X_ERR("unknown storm\n");
}
return -EINVAL;
}
static int bnx2x_mc_assert(struct bnx2x *bp)
{
char last_idx;
int i, rc = 0;
u32 row0, row1, row2, row3;
/* XSTORM */
last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
XSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx)
BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
/* print the asserts */
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
XSTORM_ASSERT_LIST_OFFSET(i));
row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
XSTORM_ASSERT_LIST_OFFSET(i) + 4);
row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
XSTORM_ASSERT_LIST_OFFSET(i) + 8);
row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
XSTORM_ASSERT_LIST_OFFSET(i) + 12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, row3, row2, row1, row0);
rc++;
} else {
break;
}
}
/* TSTORM */
last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
TSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx)
BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
/* print the asserts */
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
TSTORM_ASSERT_LIST_OFFSET(i));
row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
TSTORM_ASSERT_LIST_OFFSET(i) + 4);
row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
TSTORM_ASSERT_LIST_OFFSET(i) + 8);
row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
TSTORM_ASSERT_LIST_OFFSET(i) + 12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, row3, row2, row1, row0);
rc++;
} else {
break;
}
}
int i, j, rc = 0;
enum storms storm;
u32 regs[REGS_IN_ENTRY];
u32 bar_storm_intmem[STORMS_NUM] = {
BAR_XSTRORM_INTMEM,
BAR_TSTRORM_INTMEM,
BAR_CSTRORM_INTMEM,
BAR_USTRORM_INTMEM
};
u32 storm_assert_list_index[STORMS_NUM] = {
XSTORM_ASSERT_LIST_INDEX_OFFSET,
TSTORM_ASSERT_LIST_INDEX_OFFSET,
CSTORM_ASSERT_LIST_INDEX_OFFSET,
USTORM_ASSERT_LIST_INDEX_OFFSET
};
char *storms_string[STORMS_NUM] = {
"XSTORM",
"TSTORM",
"CSTORM",
"USTORM"
};
/* CSTORM */
last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
CSTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx)
BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
/* print the asserts */
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
CSTORM_ASSERT_LIST_OFFSET(i));
row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
CSTORM_ASSERT_LIST_OFFSET(i) + 4);
row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
CSTORM_ASSERT_LIST_OFFSET(i) + 8);
row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
CSTORM_ASSERT_LIST_OFFSET(i) + 12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, row3, row2, row1, row0);
rc++;
} else {
break;
for (storm = XSTORM; storm < MAX_STORMS; storm++) {
last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
storm_assert_list_index[storm]);
if (last_idx)
BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
storms_string[storm], last_idx);
/* print the asserts */
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
/* read a single assert entry */
for (j = 0; j < REGS_IN_ENTRY; j++)
regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
bnx2x_get_assert_list_entry(bp,
storm,
i) +
sizeof(u32) * j);
/* log entry if it contains a valid assert */
if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
storms_string[storm], i, regs[3],
regs[2], regs[1], regs[0]);
rc++;
} else {
break;
}
}
}
/* USTORM */
last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
USTORM_ASSERT_LIST_INDEX_OFFSET);
if (last_idx)
BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
/* print the asserts */
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
USTORM_ASSERT_LIST_OFFSET(i));
row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
USTORM_ASSERT_LIST_OFFSET(i) + 4);
row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
USTORM_ASSERT_LIST_OFFSET(i) + 8);
row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
USTORM_ASSERT_LIST_OFFSET(i) + 12);
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, row3, row2, row1, row0);
rc++;
} else {
break;
}
}
BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
CHIP_IS_E1(bp) ? "everest1" :
CHIP_IS_E1H(bp) ? "everest1h" :
CHIP_IS_E2(bp) ? "everest2" : "everest3",
BCM_5710_FW_MAJOR_VERSION,
BCM_5710_FW_MINOR_VERSION,
BCM_5710_FW_REVISION_VERSION);
return rc;
}
......
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