clk: aspeed: Add platform driver and register PLLs
This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Reviewed-by:Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
Joel Stanley <joel@jms.id.au> Reviewed-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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