Commit 9b6f2098 authored by Patrik Jakobsson's avatar Patrik Jakobsson Committed by Jani Nikula

drm/i915/gen9: Check for DC state mismatch

The DMC can incorrectly run off and allow DC states on it's own. We
don't know the root-cause for this yet but this patch makes it more
visible.
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarPatrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-2-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 832dba88)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 53188eb4
...@@ -751,6 +751,7 @@ struct intel_csr { ...@@ -751,6 +751,7 @@ struct intel_csr {
uint32_t mmio_count; uint32_t mmio_count;
i915_reg_t mmioaddr[8]; i915_reg_t mmioaddr[8];
uint32_t mmiodata[8]; uint32_t mmiodata[8];
uint32_t dc_state;
}; };
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \ #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
......
...@@ -240,6 +240,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) ...@@ -240,6 +240,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
I915_WRITE(dev_priv->csr.mmioaddr[i], I915_WRITE(dev_priv->csr.mmioaddr[i],
dev_priv->csr.mmiodata[i]); dev_priv->csr.mmiodata[i]);
} }
dev_priv->csr.dc_state = 0;
} }
static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
......
...@@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) ...@@ -494,10 +494,18 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
val = I915_READ(DC_STATE_EN); val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
val & mask, state); val & mask, state);
/* Check if DMC is ignoring our DC state requests */
if ((val & mask) != dev_priv->csr.dc_state)
DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
dev_priv->csr.dc_state, val & mask);
val &= ~mask; val &= ~mask;
val |= state; val |= state;
I915_WRITE(DC_STATE_EN, val); I915_WRITE(DC_STATE_EN, val);
POSTING_READ(DC_STATE_EN); POSTING_READ(DC_STATE_EN);
dev_priv->csr.dc_state = val & mask;
} }
void bxt_enable_dc9(struct drm_i915_private *dev_priv) void bxt_enable_dc9(struct drm_i915_private *dev_priv)
......
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