Commit 9ed5c17d authored by Scott Wood's avatar Scott Wood Committed by Shawn Guo

arm64: dts: ls1012a: Add coreclk

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Accordingly, update the clock-frequency in sysclk to 125M as platform
input clock.
Signed-off-by: default avatarScott Wood <oss@buserror.net>
Signed-off-by: default avatarTang Yuantian <andy.tang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0fc9a691
......@@ -76,10 +76,17 @@ cpu0: cpu@0 {
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-frequency = <125000000>;
clock-output-names = "sysclk";
};
coreclk: coreclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "coreclk";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
......@@ -248,7 +255,8 @@ clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
clocks = <&sysclk &coreclk>;
clock-names = "sysclk", "coreclk";
};
tmu: tmu@1f00000 {
......
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