Commit a08ac5a6 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher

drm/amd/display: Add pp_smu null pointer check

res_pool->pp_smu may be NULL. Check before use
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 69226e9c
...@@ -1391,12 +1391,14 @@ void dcn_bw_update_from_pplib(struct dc *dc) ...@@ -1391,12 +1391,14 @@ void dcn_bw_update_from_pplib(struct dc *dc)
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
{ {
struct pp_smu_funcs_rv *pp = &dc->res_pool->pp_smu->rv_funcs; struct pp_smu_funcs_rv *pp = NULL;
struct pp_smu_wm_range_sets ranges = {0}; struct pp_smu_wm_range_sets ranges = {0};
int min_fclk_khz, min_dcfclk_khz, socclk_khz; int min_fclk_khz, min_dcfclk_khz, socclk_khz;
const int overdrive = 5000000; /* 5 GHz to cover Overdrive */ const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
if (!pp->set_wm_ranges) if (dc->res_pool->pp_smu)
pp = &dc->res_pool->pp_smu->rv_funcs;
if (!pp || !pp->set_wm_ranges)
return; return;
kernel_fpu_begin(); kernel_fpu_begin();
......
...@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, ...@@ -171,7 +171,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
struct pp_smu_display_requirement_rv *smu_req_cur = struct pp_smu_display_requirement_rv *smu_req_cur =
&dc->res_pool->pp_smu_req; &dc->res_pool->pp_smu_req;
struct pp_smu_display_requirement_rv smu_req = *smu_req_cur; struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
struct pp_smu_funcs_rv *pp_smu = &dc->res_pool->pp_smu->rv_funcs; struct pp_smu_funcs_rv *pp_smu = NULL;
bool send_request_to_increase = false; bool send_request_to_increase = false;
bool send_request_to_lower = false; bool send_request_to_lower = false;
int display_count; int display_count;
...@@ -179,7 +179,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, ...@@ -179,7 +179,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
bool enter_display_off = false; bool enter_display_off = false;
display_count = get_active_display_cnt(dc, context); display_count = get_active_display_cnt(dc, context);
if (dc->res_pool->pp_smu)
pp_smu = &dc->res_pool->pp_smu->rv_funcs;
if (display_count == 0) if (display_count == 0)
enter_display_off = true; enter_display_off = true;
...@@ -189,7 +190,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, ...@@ -189,7 +190,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
* if function pointer not set up, this message is * if function pointer not set up, this message is
* sent as part of pplib_apply_display_requirements. * sent as part of pplib_apply_display_requirements.
*/ */
if (pp_smu->set_display_count) if (pp_smu && pp_smu->set_display_count)
pp_smu->set_display_count(&pp_smu->pp_smu, display_count); pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
smu_req.display_count = display_count; smu_req.display_count = display_count;
...@@ -239,7 +240,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, ...@@ -239,7 +240,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
*/ */
if (send_request_to_increase) { if (send_request_to_increase) {
/*use dcfclk to request voltage*/ /*use dcfclk to request voltage*/
if (pp_smu->set_hard_min_fclk_by_freq && if (pp_smu && pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq && pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) { pp_smu->set_min_deep_sleep_dcfclk) {
...@@ -261,7 +262,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr, ...@@ -261,7 +262,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
if (!send_request_to_increase && send_request_to_lower) { if (!send_request_to_increase && send_request_to_lower) {
/*use dcfclk to request voltage*/ /*use dcfclk to request voltage*/
if (pp_smu->set_hard_min_fclk_by_freq && if (pp_smu && pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq && pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) { pp_smu->set_min_deep_sleep_dcfclk) {
......
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