Commit a1409ada authored by Alistair Popple's avatar Alistair Popple Committed by Michael Ellerman

powerpc/powernv/npu: Prevent overwriting of pnv_npu2_init_contex() callback parameters

There is a single npu context per set of callback parameters. Callers
should be prevented from overwriting existing callback values so
instead return an error if different parameters are passed.

Fixes: 1ab66d1f ("powerpc/powernv: Introduce address translation services for Nvlink2")
Cc: stable@vger.kernel.org # v4.12+
Signed-off-by: default avatarAlistair Popple <alistair@popple.id.au>
Reviewed-by: default avatarMark Hairgrove <mhairgrove@nvidia.com>
Tested-by: default avatarMark Hairgrove <mhairgrove@nvidia.com>
Reviewed-by: default avatarBalbir Singh <bsingharora@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 28a5933e
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
extern void powernv_set_nmmu_ptcr(unsigned long ptcr); extern void powernv_set_nmmu_ptcr(unsigned long ptcr);
extern struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev, extern struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
unsigned long flags, unsigned long flags,
struct npu_context *(*cb)(struct npu_context *, void *), void (*cb)(struct npu_context *, void *),
void *priv); void *priv);
extern void pnv_npu2_destroy_context(struct npu_context *context, extern void pnv_npu2_destroy_context(struct npu_context *context,
struct pci_dev *gpdev); struct pci_dev *gpdev);
......
...@@ -407,7 +407,7 @@ struct npu_context { ...@@ -407,7 +407,7 @@ struct npu_context {
bool nmmu_flush; bool nmmu_flush;
/* Callback to stop translation requests on a given GPU */ /* Callback to stop translation requests on a given GPU */
struct npu_context *(*release_cb)(struct npu_context *, void *); void (*release_cb)(struct npu_context *context, void *priv);
/* /*
* Private pointer passed to the above callback for usage by * Private pointer passed to the above callback for usage by
...@@ -707,7 +707,7 @@ static const struct mmu_notifier_ops nv_nmmu_notifier_ops = { ...@@ -707,7 +707,7 @@ static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
*/ */
struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev, struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
unsigned long flags, unsigned long flags,
struct npu_context *(*cb)(struct npu_context *, void *), void (*cb)(struct npu_context *, void *),
void *priv) void *priv)
{ {
int rc; int rc;
...@@ -765,8 +765,18 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev, ...@@ -765,8 +765,18 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
*/ */
spin_lock(&npu_context_lock); spin_lock(&npu_context_lock);
npu_context = mm->context.npu_context; npu_context = mm->context.npu_context;
if (npu_context) if (npu_context) {
if (npu_context->release_cb != cb ||
npu_context->priv != priv) {
spin_unlock(&npu_context_lock);
opal_npu_destroy_context(nphb->opal_id, mm->context.id,
PCI_DEVID(gpdev->bus->number,
gpdev->devfn));
return ERR_PTR(-EINVAL);
}
WARN_ON(!kref_get_unless_zero(&npu_context->kref)); WARN_ON(!kref_get_unless_zero(&npu_context->kref));
}
spin_unlock(&npu_context_lock); spin_unlock(&npu_context_lock);
if (!npu_context) { if (!npu_context) {
......
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